435 lines
9.4 KiB
C
435 lines
9.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
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* Author: Jacob Chen <jacob-chen@iotwrt.com>
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*/
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#ifndef __RGA_HW_H__
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#define __RGA_HW_H__
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#define RGA_CMDBUF_SIZE 0x20
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/* Hardware limits */
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#define MAX_WIDTH 8192
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#define MAX_HEIGHT 8192
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#define MIN_WIDTH 34
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#define MIN_HEIGHT 34
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#define DEFAULT_WIDTH 100
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#define DEFAULT_HEIGHT 100
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#define RGA_TIMEOUT 500
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/* Registers address */
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#define RGA_SYS_CTRL 0x0000
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#define RGA_CMD_CTRL 0x0004
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#define RGA_CMD_BASE 0x0008
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#define RGA_INT 0x0010
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#define RGA_MMU_CTRL0 0x0014
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#define RGA_VERSION_INFO 0x0028
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#define RGA_MODE_BASE_REG 0x0100
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#define RGA_MODE_MAX_REG 0x017C
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#define RGA_MODE_CTRL 0x0100
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#define RGA_SRC_INFO 0x0104
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#define RGA_SRC_Y_RGB_BASE_ADDR 0x0108
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#define RGA_SRC_CB_BASE_ADDR 0x010c
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#define RGA_SRC_CR_BASE_ADDR 0x0110
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#define RGA_SRC1_RGB_BASE_ADDR 0x0114
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#define RGA_SRC_VIR_INFO 0x0118
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#define RGA_SRC_ACT_INFO 0x011c
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#define RGA_SRC_X_FACTOR 0x0120
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#define RGA_SRC_Y_FACTOR 0x0124
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#define RGA_SRC_BG_COLOR 0x0128
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#define RGA_SRC_FG_COLOR 0x012c
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#define RGA_SRC_TR_COLOR0 0x0130
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#define RGA_SRC_TR_COLOR1 0x0134
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#define RGA_DST_INFO 0x0138
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#define RGA_DST_Y_RGB_BASE_ADDR 0x013c
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#define RGA_DST_CB_BASE_ADDR 0x0140
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#define RGA_DST_CR_BASE_ADDR 0x0144
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#define RGA_DST_VIR_INFO 0x0148
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#define RGA_DST_ACT_INFO 0x014c
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#define RGA_ALPHA_CTRL0 0x0150
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#define RGA_ALPHA_CTRL1 0x0154
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#define RGA_FADING_CTRL 0x0158
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#define RGA_PAT_CON 0x015c
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#define RGA_ROP_CON0 0x0160
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#define RGA_ROP_CON1 0x0164
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#define RGA_MASK_BASE 0x0168
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#define RGA_MMU_CTRL1 0x016C
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#define RGA_MMU_SRC_BASE 0x0170
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#define RGA_MMU_SRC1_BASE 0x0174
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#define RGA_MMU_DST_BASE 0x0178
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/* Registers value */
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#define RGA_MODE_RENDER_BITBLT 0
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#define RGA_MODE_RENDER_COLOR_PALETTE 1
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#define RGA_MODE_RENDER_RECTANGLE_FILL 2
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#define RGA_MODE_RENDER_UPDATE_PALETTE_LUT_RAM 3
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#define RGA_MODE_BITBLT_MODE_SRC_TO_DST 0
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#define RGA_MODE_BITBLT_MODE_SRC_SRC1_TO_DST 1
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#define RGA_MODE_CF_ROP4_SOLID 0
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#define RGA_MODE_CF_ROP4_PATTERN 1
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#define RGA_COLOR_FMT_ABGR8888 0
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#define RGA_COLOR_FMT_XBGR8888 1
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#define RGA_COLOR_FMT_RGB888 2
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#define RGA_COLOR_FMT_BGR565 4
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#define RGA_COLOR_FMT_ABGR1555 5
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#define RGA_COLOR_FMT_ABGR4444 6
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#define RGA_COLOR_FMT_YUV422SP 8
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#define RGA_COLOR_FMT_YUV422P 9
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#define RGA_COLOR_FMT_YUV420SP 10
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#define RGA_COLOR_FMT_YUV420P 11
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/* SRC_COLOR Palette */
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#define RGA_COLOR_FMT_CP_1BPP 12
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#define RGA_COLOR_FMT_CP_2BPP 13
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#define RGA_COLOR_FMT_CP_4BPP 14
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#define RGA_COLOR_FMT_CP_8BPP 15
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#define RGA_COLOR_FMT_MASK 15
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#define RGA_COLOR_FMT_IS_YUV(fmt) \
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(((fmt) >= RGA_COLOR_FMT_YUV422SP) && ((fmt) < RGA_COLOR_FMT_CP_1BPP))
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#define RGA_COLOR_FMT_IS_RGB(fmt) \
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((fmt) < RGA_COLOR_FMT_YUV422SP)
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#define RGA_COLOR_NONE_SWAP 0
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#define RGA_COLOR_RB_SWAP 1
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#define RGA_COLOR_ALPHA_SWAP 2
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#define RGA_COLOR_UV_SWAP 4
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#define RGA_SRC_CSC_MODE_BYPASS 0
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#define RGA_SRC_CSC_MODE_BT601_R0 1
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#define RGA_SRC_CSC_MODE_BT601_R1 2
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#define RGA_SRC_CSC_MODE_BT709_R0 3
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#define RGA_SRC_CSC_MODE_BT709_R1 4
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#define RGA_SRC_ROT_MODE_0_DEGREE 0
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#define RGA_SRC_ROT_MODE_90_DEGREE 1
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#define RGA_SRC_ROT_MODE_180_DEGREE 2
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#define RGA_SRC_ROT_MODE_270_DEGREE 3
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#define RGA_SRC_MIRR_MODE_NO 0
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#define RGA_SRC_MIRR_MODE_X 1
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#define RGA_SRC_MIRR_MODE_Y 2
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#define RGA_SRC_MIRR_MODE_X_Y 3
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#define RGA_SRC_HSCL_MODE_NO 0
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#define RGA_SRC_HSCL_MODE_DOWN 1
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#define RGA_SRC_HSCL_MODE_UP 2
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#define RGA_SRC_VSCL_MODE_NO 0
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#define RGA_SRC_VSCL_MODE_DOWN 1
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#define RGA_SRC_VSCL_MODE_UP 2
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#define RGA_SRC_TRANS_ENABLE_R 1
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#define RGA_SRC_TRANS_ENABLE_G 2
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#define RGA_SRC_TRANS_ENABLE_B 4
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#define RGA_SRC_TRANS_ENABLE_A 8
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#define RGA_SRC_BIC_COE_SELEC_CATROM 0
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#define RGA_SRC_BIC_COE_SELEC_MITCHELL 1
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#define RGA_SRC_BIC_COE_SELEC_HERMITE 2
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#define RGA_SRC_BIC_COE_SELEC_BSPLINE 3
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#define RGA_DST_DITHER_MODE_888_TO_666 0
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#define RGA_DST_DITHER_MODE_888_TO_565 1
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#define RGA_DST_DITHER_MODE_888_TO_555 2
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#define RGA_DST_DITHER_MODE_888_TO_444 3
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#define RGA_DST_CSC_MODE_BYPASS 0
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#define RGA_DST_CSC_MODE_BT601_R0 1
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#define RGA_DST_CSC_MODE_BT601_R1 2
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#define RGA_DST_CSC_MODE_BT709_R0 3
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#define RGA_ALPHA_ROP_MODE_2 0
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#define RGA_ALPHA_ROP_MODE_3 1
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#define RGA_ALPHA_ROP_MODE_4 2
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#define RGA_ALPHA_SELECT_ALPHA 0
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#define RGA_ALPHA_SELECT_ROP 1
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#define RGA_ALPHA_MASK_BIG_ENDIAN 0
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#define RGA_ALPHA_MASK_LITTLE_ENDIAN 1
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#define RGA_ALPHA_NORMAL 0
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#define RGA_ALPHA_REVERSE 1
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#define RGA_ALPHA_BLEND_GLOBAL 0
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#define RGA_ALPHA_BLEND_NORMAL 1
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#define RGA_ALPHA_BLEND_MULTIPLY 2
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#define RGA_ALPHA_CAL_CUT 0
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#define RGA_ALPHA_CAL_NORMAL 1
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#define RGA_ALPHA_FACTOR_ZERO 0
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#define RGA_ALPHA_FACTOR_ONE 1
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#define RGA_ALPHA_FACTOR_OTHER 2
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#define RGA_ALPHA_FACTOR_OTHER_REVERSE 3
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#define RGA_ALPHA_FACTOR_SELF 4
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#define RGA_ALPHA_COLOR_NORMAL 0
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#define RGA_ALPHA_COLOR_MULTIPLY_CAL 1
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/* Registers union */
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union rga_mode_ctrl {
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unsigned int val;
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struct {
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/* [0:2] */
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unsigned int render:3;
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/* [3:6] */
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unsigned int bitblt:1;
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unsigned int cf_rop4_pat:1;
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unsigned int alpha_zero_key:1;
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unsigned int gradient_sat:1;
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/* [7:31] */
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unsigned int reserved:25;
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} data;
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};
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union rga_src_info {
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unsigned int val;
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struct {
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/* [0:3] */
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unsigned int format:4;
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/* [4:7] */
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unsigned int swap:3;
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unsigned int cp_endian:1;
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/* [8:17] */
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unsigned int csc_mode:2;
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unsigned int rot_mode:2;
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unsigned int mir_mode:2;
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unsigned int hscl_mode:2;
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unsigned int vscl_mode:2;
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/* [18:22] */
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unsigned int trans_mode:1;
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unsigned int trans_enable:4;
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/* [23:25] */
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unsigned int dither_up_en:1;
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unsigned int bic_coe_sel:2;
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/* [26:31] */
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unsigned int reserved:6;
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} data;
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};
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union rga_src_vir_info {
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unsigned int val;
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struct {
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/* [0:15] */
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unsigned int vir_width:15;
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unsigned int reserved:1;
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/* [16:25] */
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unsigned int vir_stride:10;
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/* [26:31] */
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unsigned int reserved1:6;
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} data;
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};
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union rga_src_act_info {
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unsigned int val;
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struct {
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/* [0:15] */
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unsigned int act_width:13;
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unsigned int reserved:3;
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/* [16:31] */
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unsigned int act_height:13;
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unsigned int reserved1:3;
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} data;
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};
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union rga_src_x_factor {
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unsigned int val;
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struct {
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/* [0:15] */
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unsigned int down_scale_factor:16;
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/* [16:31] */
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unsigned int up_scale_factor:16;
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} data;
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};
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union rga_src_y_factor {
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unsigned int val;
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struct {
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/* [0:15] */
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unsigned int down_scale_factor:16;
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/* [16:31] */
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unsigned int up_scale_factor:16;
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} data;
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};
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/* Alpha / Red / Green / Blue */
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union rga_src_cp_gr_color {
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unsigned int val;
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struct {
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/* [0:15] */
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unsigned int gradient_x:16;
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/* [16:31] */
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unsigned int gradient_y:16;
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} data;
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};
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union rga_src_transparency_color0 {
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unsigned int val;
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struct {
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/* [0:7] */
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unsigned int trans_rmin:8;
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/* [8:15] */
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unsigned int trans_gmin:8;
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/* [16:23] */
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unsigned int trans_bmin:8;
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/* [24:31] */
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unsigned int trans_amin:8;
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} data;
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};
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union rga_src_transparency_color1 {
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unsigned int val;
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struct {
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/* [0:7] */
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unsigned int trans_rmax:8;
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/* [8:15] */
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unsigned int trans_gmax:8;
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/* [16:23] */
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unsigned int trans_bmax:8;
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/* [24:31] */
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unsigned int trans_amax:8;
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} data;
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};
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union rga_dst_info {
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unsigned int val;
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struct {
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/* [0:3] */
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unsigned int format:4;
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/* [4:6] */
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unsigned int swap:3;
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/* [7:9] */
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unsigned int src1_format:3;
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/* [10:11] */
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unsigned int src1_swap:2;
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/* [12:15] */
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unsigned int dither_up_en:1;
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unsigned int dither_down_en:1;
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unsigned int dither_down_mode:2;
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/* [16:18] */
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unsigned int csc_mode:2;
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unsigned int csc_clip:1;
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/* [19:31] */
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unsigned int reserved:13;
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} data;
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};
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union rga_dst_vir_info {
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unsigned int val;
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struct {
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/* [0:15] */
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unsigned int vir_stride:15;
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unsigned int reserved:1;
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/* [16:31] */
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unsigned int src1_vir_stride:15;
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unsigned int reserved1:1;
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} data;
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};
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union rga_dst_act_info {
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unsigned int val;
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struct {
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/* [0:15] */
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unsigned int act_width:12;
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unsigned int reserved:4;
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/* [16:31] */
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unsigned int act_height:12;
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unsigned int reserved1:4;
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} data;
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};
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union rga_alpha_ctrl0 {
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unsigned int val;
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struct {
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/* [0:3] */
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unsigned int rop_en:1;
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unsigned int rop_select:1;
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unsigned int rop_mode:2;
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/* [4:11] */
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unsigned int src_fading_val:8;
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/* [12:20] */
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unsigned int dst_fading_val:8;
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unsigned int mask_endian:1;
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/* [21:31] */
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unsigned int reserved:11;
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} data;
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};
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union rga_alpha_ctrl1 {
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unsigned int val;
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struct {
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/* [0:1] */
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unsigned int dst_color_m0:1;
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unsigned int src_color_m0:1;
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/* [2:7] */
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unsigned int dst_factor_m0:3;
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unsigned int src_factor_m0:3;
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/* [8:9] */
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unsigned int dst_alpha_cal_m0:1;
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unsigned int src_alpha_cal_m0:1;
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/* [10:13] */
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unsigned int dst_blend_m0:2;
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unsigned int src_blend_m0:2;
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/* [14:15] */
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unsigned int dst_alpha_m0:1;
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unsigned int src_alpha_m0:1;
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/* [16:21] */
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unsigned int dst_factor_m1:3;
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unsigned int src_factor_m1:3;
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/* [22:23] */
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unsigned int dst_alpha_cal_m1:1;
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unsigned int src_alpha_cal_m1:1;
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/* [24:27] */
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unsigned int dst_blend_m1:2;
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unsigned int src_blend_m1:2;
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/* [28:29] */
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unsigned int dst_alpha_m1:1;
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unsigned int src_alpha_m1:1;
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/* [30:31] */
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unsigned int reserved:2;
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} data;
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};
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union rga_fading_ctrl {
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unsigned int val;
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struct {
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/* [0:7] */
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unsigned int fading_offset_r:8;
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/* [8:15] */
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unsigned int fading_offset_g:8;
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/* [16:23] */
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unsigned int fading_offset_b:8;
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/* [24:31] */
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unsigned int fading_en:1;
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unsigned int reserved:7;
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} data;
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};
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union rga_pat_con {
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unsigned int val;
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struct {
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/* [0:7] */
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unsigned int width:8;
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/* [8:15] */
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unsigned int height:8;
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/* [16:23] */
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unsigned int offset_x:8;
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/* [24:31] */
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unsigned int offset_y:8;
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} data;
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};
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#endif
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