145 lines
3.6 KiB
C
145 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2002 ARM Limited, All Rights Reserved.
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*/
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip/arm-gic.h>
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#include "irq-gic-common.h"
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static DEFINE_RAW_SPINLOCK(irq_controller_lock);
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void gic_enable_of_quirks(const struct device_node *np,
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const struct gic_quirk *quirks, void *data)
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{
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for (; quirks->desc; quirks++) {
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if (!of_device_is_compatible(np, quirks->compatible))
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continue;
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if (quirks->init(data))
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pr_info("GIC: enabling workaround for %s\n",
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quirks->desc);
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}
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}
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void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks,
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void *data)
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{
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for (; quirks->desc; quirks++) {
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if (quirks->compatible)
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continue;
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if (quirks->iidr != (quirks->mask & iidr))
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continue;
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if (quirks->init(data))
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pr_info("GIC: enabling workaround for %s\n",
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quirks->desc);
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}
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}
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int gic_configure_irq(unsigned int irq, unsigned int type,
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void __iomem *base, void (*sync_access)(void))
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{
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u32 confmask = 0x2 << ((irq % 16) * 2);
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u32 confoff = (irq / 16) * 4;
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u32 val, oldval;
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int ret = 0;
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unsigned long flags;
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/*
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* Read current configuration register, and insert the config
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* for "irq", depending on "type".
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*/
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raw_spin_lock_irqsave(&irq_controller_lock, flags);
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val = oldval = readl_relaxed(base + confoff);
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if (type & IRQ_TYPE_LEVEL_MASK)
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val &= ~confmask;
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else if (type & IRQ_TYPE_EDGE_BOTH)
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val |= confmask;
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/* If the current configuration is the same, then we are done */
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if (val == oldval) {
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raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
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return 0;
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}
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/*
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* Write back the new configuration, and possibly re-enable
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* the interrupt. If we fail to write a new configuration for
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* an SPI then WARN and return an error. If we fail to write the
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* configuration for a PPI this is most likely because the GIC
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* does not allow us to set the configuration or we are in a
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* non-secure mode, and hence it may not be catastrophic.
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*/
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writel_relaxed(val, base + confoff);
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if (readl_relaxed(base + confoff) != val)
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ret = -EINVAL;
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raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
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if (sync_access)
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sync_access();
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return ret;
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}
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void gic_dist_config(void __iomem *base, int gic_irqs,
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void (*sync_access)(void))
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{
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unsigned int i;
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/*
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* Set all global interrupts to be level triggered, active low.
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*/
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for (i = 32; i < gic_irqs; i += 16)
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writel_relaxed(GICD_INT_ACTLOW_LVLTRIG,
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base + GIC_DIST_CONFIG + i / 4);
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/*
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* Set priority on all global interrupts.
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*/
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for (i = 32; i < gic_irqs; i += 4)
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writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i);
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/*
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* Deactivate and disable all SPIs. Leave the PPI and SGIs
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* alone as they are in the redistributor registers on GICv3.
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*/
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for (i = 32; i < gic_irqs; i += 32) {
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writel_relaxed(GICD_INT_EN_CLR_X32,
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base + GIC_DIST_ACTIVE_CLEAR + i / 8);
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writel_relaxed(GICD_INT_EN_CLR_X32,
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base + GIC_DIST_ENABLE_CLEAR + i / 8);
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}
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if (sync_access)
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sync_access();
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}
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void gic_cpu_config(void __iomem *base, int nr, void (*sync_access)(void))
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{
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int i;
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/*
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* Deal with the banked PPI and SGI interrupts - disable all
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* private interrupts. Make sure everything is deactivated.
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*/
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for (i = 0; i < nr; i += 32) {
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writel_relaxed(GICD_INT_EN_CLR_X32,
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base + GIC_DIST_ACTIVE_CLEAR + i / 8);
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writel_relaxed(GICD_INT_EN_CLR_X32,
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base + GIC_DIST_ENABLE_CLEAR + i / 8);
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}
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/*
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* Set priority on PPI and SGI interrupts
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*/
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for (i = 0; i < nr; i += 4)
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writel_relaxed(GICD_INT_DEF_PRI_X4,
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base + GIC_DIST_PRI + i * 4 / 4);
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if (sync_access)
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sync_access();
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}
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