675 lines
17 KiB
C
675 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Analog Devices AD5766, AD5767
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* Digital to Analog Converters driver
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* Copyright 2019-2020 Analog Devices Inc.
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*/
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/gpio/consumer.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/triggered_buffer.h>
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#include <linux/iio/trigger_consumer.h>
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#include <linux/module.h>
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#include <linux/spi/spi.h>
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#include <asm/unaligned.h>
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#define AD5766_UPPER_WORD_SPI_MASK GENMASK(31, 16)
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#define AD5766_LOWER_WORD_SPI_MASK GENMASK(15, 0)
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#define AD5766_DITHER_SOURCE_MASK(ch) GENMASK(((2 * ch) + 1), (2 * ch))
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#define AD5766_DITHER_SOURCE(ch, source) BIT((ch * 2) + source)
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#define AD5766_DITHER_SCALE_MASK(x) AD5766_DITHER_SOURCE_MASK(x)
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#define AD5766_DITHER_SCALE(ch, scale) (scale << (ch * 2))
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#define AD5766_DITHER_ENABLE_MASK(ch) BIT(ch)
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#define AD5766_DITHER_ENABLE(ch, state) ((!state) << ch)
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#define AD5766_DITHER_INVERT_MASK(ch) BIT(ch)
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#define AD5766_DITHER_INVERT(ch, state) (state << ch)
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#define AD5766_CMD_NOP_MUX_OUT 0x00
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#define AD5766_CMD_SDO_CNTRL 0x01
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#define AD5766_CMD_WR_IN_REG(x) (0x10 | ((x) & GENMASK(3, 0)))
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#define AD5766_CMD_WR_DAC_REG(x) (0x20 | ((x) & GENMASK(3, 0)))
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#define AD5766_CMD_SW_LDAC 0x30
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#define AD5766_CMD_SPAN_REG 0x40
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#define AD5766_CMD_WR_PWR_DITHER 0x51
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#define AD5766_CMD_WR_DAC_REG_ALL 0x60
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#define AD5766_CMD_SW_FULL_RESET 0x70
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#define AD5766_CMD_READBACK_REG(x) (0x80 | ((x) & GENMASK(3, 0)))
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#define AD5766_CMD_DITHER_SIG_1 0x90
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#define AD5766_CMD_DITHER_SIG_2 0xA0
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#define AD5766_CMD_INV_DITHER 0xB0
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#define AD5766_CMD_DITHER_SCALE_1 0xC0
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#define AD5766_CMD_DITHER_SCALE_2 0xD0
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#define AD5766_FULL_RESET_CODE 0x1234
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enum ad5766_type {
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ID_AD5766,
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ID_AD5767,
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};
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enum ad5766_voltage_range {
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AD5766_VOLTAGE_RANGE_M20V_0V,
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AD5766_VOLTAGE_RANGE_M16V_to_0V,
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AD5766_VOLTAGE_RANGE_M10V_to_0V,
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AD5766_VOLTAGE_RANGE_M12V_to_14V,
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AD5766_VOLTAGE_RANGE_M16V_to_10V,
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AD5766_VOLTAGE_RANGE_M10V_to_6V,
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AD5766_VOLTAGE_RANGE_M5V_to_5V,
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AD5766_VOLTAGE_RANGE_M10V_to_10V,
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};
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/**
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* struct ad5766_chip_info - chip specific information
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* @num_channels: number of channels
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* @channels: channel specification
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*/
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struct ad5766_chip_info {
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unsigned int num_channels;
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const struct iio_chan_spec *channels;
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};
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enum {
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AD5766_DITHER_ENABLE,
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AD5766_DITHER_INVERT,
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AD5766_DITHER_SOURCE,
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};
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/*
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* Dither signal can also be scaled.
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* Available dither scale strings corresponding to "dither_scale" field in
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* "struct ad5766_state".
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*/
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static const char * const ad5766_dither_scales[] = {
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"1",
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"0.75",
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"0.5",
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"0.25",
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};
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/**
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* struct ad5766_state - driver instance specific data
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* @spi: SPI device
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* @lock: Lock used to restrict concurrent access to SPI device
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* @chip_info: Chip model specific constants
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* @gpio_reset: Reset GPIO, used to reset the device
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* @crt_range: Current selected output range
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* @dither_enable: Power enable bit for each channel dither block (for
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* example, D15 = DAC 15,D8 = DAC 8, and D0 = DAC 0)
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* 0 - Normal operation, 1 - Power down
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* @dither_invert: Inverts the dither signal applied to the selected DAC
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* outputs
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* @dither_source: Selects between 2 possible sources:
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* 1: N0, 2: N1
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* Two bits are used for each channel
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* @dither_scale: Two bits are used for each of the 16 channels:
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* 0: 1 SCALING, 1: 0.75 SCALING, 2: 0.5 SCALING,
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* 3: 0.25 SCALING.
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* @data: SPI transfer buffers
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*/
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struct ad5766_state {
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struct spi_device *spi;
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struct mutex lock;
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const struct ad5766_chip_info *chip_info;
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struct gpio_desc *gpio_reset;
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enum ad5766_voltage_range crt_range;
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u16 dither_enable;
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u16 dither_invert;
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u32 dither_source;
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u32 dither_scale;
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union {
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u32 d32;
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u16 w16[2];
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u8 b8[4];
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} data[3] ____cacheline_aligned;
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};
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struct ad5766_span_tbl {
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int min;
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int max;
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};
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static const struct ad5766_span_tbl ad5766_span_tbl[] = {
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[AD5766_VOLTAGE_RANGE_M20V_0V] = {-20, 0},
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[AD5766_VOLTAGE_RANGE_M16V_to_0V] = {-16, 0},
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[AD5766_VOLTAGE_RANGE_M10V_to_0V] = {-10, 0},
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[AD5766_VOLTAGE_RANGE_M12V_to_14V] = {-12, 14},
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[AD5766_VOLTAGE_RANGE_M16V_to_10V] = {-16, 10},
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[AD5766_VOLTAGE_RANGE_M10V_to_6V] = {-10, 6},
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[AD5766_VOLTAGE_RANGE_M5V_to_5V] = {-5, 5},
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[AD5766_VOLTAGE_RANGE_M10V_to_10V] = {-10, 10},
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};
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static int __ad5766_spi_read(struct ad5766_state *st, u8 dac, int *val)
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{
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int ret;
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struct spi_transfer xfers[] = {
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{
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.tx_buf = &st->data[0].d32,
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.bits_per_word = 8,
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.len = 3,
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.cs_change = 1,
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}, {
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.tx_buf = &st->data[1].d32,
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.rx_buf = &st->data[2].d32,
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.bits_per_word = 8,
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.len = 3,
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},
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};
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st->data[0].d32 = AD5766_CMD_READBACK_REG(dac);
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st->data[1].d32 = AD5766_CMD_NOP_MUX_OUT;
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ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers));
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if (ret)
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return ret;
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*val = st->data[2].w16[1];
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return ret;
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}
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static int __ad5766_spi_write(struct ad5766_state *st, u8 command, u16 data)
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{
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st->data[0].b8[0] = command;
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put_unaligned_be16(data, &st->data[0].b8[1]);
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return spi_write(st->spi, &st->data[0].b8[0], 3);
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}
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static int ad5766_read(struct iio_dev *indio_dev, u8 dac, int *val)
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{
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struct ad5766_state *st = iio_priv(indio_dev);
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int ret;
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mutex_lock(&st->lock);
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ret = __ad5766_spi_read(st, dac, val);
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mutex_unlock(&st->lock);
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return ret;
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}
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static int ad5766_write(struct iio_dev *indio_dev, u8 dac, u16 data)
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{
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struct ad5766_state *st = iio_priv(indio_dev);
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int ret;
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mutex_lock(&st->lock);
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ret = __ad5766_spi_write(st, AD5766_CMD_WR_DAC_REG(dac), data);
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mutex_unlock(&st->lock);
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return ret;
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}
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static int ad5766_reset(struct ad5766_state *st)
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{
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int ret;
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if (st->gpio_reset) {
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gpiod_set_value_cansleep(st->gpio_reset, 1);
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ndelay(100); /* t_reset >= 100ns */
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gpiod_set_value_cansleep(st->gpio_reset, 0);
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} else {
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ret = __ad5766_spi_write(st, AD5766_CMD_SW_FULL_RESET,
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AD5766_FULL_RESET_CODE);
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if (ret < 0)
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return ret;
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}
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/*
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* Minimum time between a reset and the subsequent successful write is
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* typically 25 ns
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*/
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ndelay(25);
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return 0;
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}
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static int ad5766_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val,
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int *val2,
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long m)
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{
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struct ad5766_state *st = iio_priv(indio_dev);
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int ret;
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switch (m) {
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case IIO_CHAN_INFO_RAW:
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ret = ad5766_read(indio_dev, chan->address, val);
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if (ret)
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return ret;
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_OFFSET:
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*val = ad5766_span_tbl[st->crt_range].min;
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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*val = ad5766_span_tbl[st->crt_range].max -
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ad5766_span_tbl[st->crt_range].min;
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*val2 = st->chip_info->channels[0].scan_type.realbits;
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return IIO_VAL_FRACTIONAL_LOG2;
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default:
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return -EINVAL;
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}
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}
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static int ad5766_write_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int val,
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int val2,
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long info)
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{
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switch (info) {
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case IIO_CHAN_INFO_RAW:
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{
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const int max_val = GENMASK(chan->scan_type.realbits - 1, 0);
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if (val > max_val || val < 0)
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return -EINVAL;
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val <<= chan->scan_type.shift;
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return ad5766_write(indio_dev, chan->address, val);
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}
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default:
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return -EINVAL;
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}
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}
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static const struct iio_info ad5766_info = {
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.read_raw = ad5766_read_raw,
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.write_raw = ad5766_write_raw,
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};
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static int ad5766_get_dither_source(struct iio_dev *dev,
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const struct iio_chan_spec *chan)
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{
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struct ad5766_state *st = iio_priv(dev);
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u32 source;
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source = st->dither_source & AD5766_DITHER_SOURCE_MASK(chan->channel);
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source = source >> (chan->channel * 2);
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source -= 1;
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return source;
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}
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static int ad5766_set_dither_source(struct iio_dev *dev,
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const struct iio_chan_spec *chan,
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unsigned int source)
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{
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struct ad5766_state *st = iio_priv(dev);
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uint16_t val;
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int ret;
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st->dither_source &= ~AD5766_DITHER_SOURCE_MASK(chan->channel);
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st->dither_source |= AD5766_DITHER_SOURCE(chan->channel, source);
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val = FIELD_GET(AD5766_LOWER_WORD_SPI_MASK, st->dither_source);
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ret = ad5766_write(dev, AD5766_CMD_DITHER_SIG_1, val);
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if (ret)
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return ret;
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val = FIELD_GET(AD5766_UPPER_WORD_SPI_MASK, st->dither_source);
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return ad5766_write(dev, AD5766_CMD_DITHER_SIG_2, val);
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}
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static int ad5766_get_dither_scale(struct iio_dev *dev,
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const struct iio_chan_spec *chan)
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{
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struct ad5766_state *st = iio_priv(dev);
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u32 scale;
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scale = st->dither_scale & AD5766_DITHER_SCALE_MASK(chan->channel);
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return (scale >> (chan->channel * 2));
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}
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static int ad5766_set_dither_scale(struct iio_dev *dev,
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const struct iio_chan_spec *chan,
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unsigned int scale)
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{
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int ret;
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struct ad5766_state *st = iio_priv(dev);
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uint16_t val;
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st->dither_scale &= ~AD5766_DITHER_SCALE_MASK(chan->channel);
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st->dither_scale |= AD5766_DITHER_SCALE(chan->channel, scale);
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val = FIELD_GET(AD5766_LOWER_WORD_SPI_MASK, st->dither_scale);
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ret = ad5766_write(dev, AD5766_CMD_DITHER_SCALE_1, val);
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if (ret)
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return ret;
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val = FIELD_GET(AD5766_UPPER_WORD_SPI_MASK, st->dither_scale);
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return ad5766_write(dev, AD5766_CMD_DITHER_SCALE_2, val);
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}
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static const struct iio_enum ad5766_dither_scale_enum = {
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.items = ad5766_dither_scales,
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.num_items = ARRAY_SIZE(ad5766_dither_scales),
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.set = ad5766_set_dither_scale,
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.get = ad5766_get_dither_scale,
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};
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static ssize_t ad5766_read_ext(struct iio_dev *indio_dev,
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uintptr_t private,
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const struct iio_chan_spec *chan,
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char *buf)
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{
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struct ad5766_state *st = iio_priv(indio_dev);
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switch (private) {
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case AD5766_DITHER_ENABLE:
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return sprintf(buf, "%u\n",
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!(st->dither_enable & BIT(chan->channel)));
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break;
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case AD5766_DITHER_INVERT:
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return sprintf(buf, "%u\n",
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!!(st->dither_invert & BIT(chan->channel)));
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break;
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case AD5766_DITHER_SOURCE:
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return sprintf(buf, "%d\n",
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ad5766_get_dither_source(indio_dev, chan));
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default:
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return -EINVAL;
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}
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}
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static ssize_t ad5766_write_ext(struct iio_dev *indio_dev,
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uintptr_t private,
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const struct iio_chan_spec *chan,
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const char *buf, size_t len)
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{
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struct ad5766_state *st = iio_priv(indio_dev);
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bool readin;
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int ret;
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ret = kstrtobool(buf, &readin);
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if (ret)
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return ret;
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switch (private) {
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case AD5766_DITHER_ENABLE:
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st->dither_enable &= ~AD5766_DITHER_ENABLE_MASK(chan->channel);
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st->dither_enable |= AD5766_DITHER_ENABLE(chan->channel,
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readin);
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ret = ad5766_write(indio_dev, AD5766_CMD_WR_PWR_DITHER,
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st->dither_enable);
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break;
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case AD5766_DITHER_INVERT:
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st->dither_invert &= ~AD5766_DITHER_INVERT_MASK(chan->channel);
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st->dither_invert |= AD5766_DITHER_INVERT(chan->channel,
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readin);
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ret = ad5766_write(indio_dev, AD5766_CMD_INV_DITHER,
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st->dither_invert);
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break;
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case AD5766_DITHER_SOURCE:
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ret = ad5766_set_dither_source(indio_dev, chan, readin);
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break;
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default:
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return -EINVAL;
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}
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return ret ? ret : len;
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}
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#define _AD5766_CHAN_EXT_INFO(_name, _what, _shared) { \
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.name = _name, \
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.read = ad5766_read_ext, \
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.write = ad5766_write_ext, \
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.private = _what, \
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.shared = _shared, \
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}
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static const struct iio_chan_spec_ext_info ad5766_ext_info[] = {
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_AD5766_CHAN_EXT_INFO("dither_enable", AD5766_DITHER_ENABLE,
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IIO_SEPARATE),
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_AD5766_CHAN_EXT_INFO("dither_invert", AD5766_DITHER_INVERT,
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IIO_SEPARATE),
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_AD5766_CHAN_EXT_INFO("dither_source", AD5766_DITHER_SOURCE,
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IIO_SEPARATE),
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IIO_ENUM("dither_scale", IIO_SEPARATE, &ad5766_dither_scale_enum),
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IIO_ENUM_AVAILABLE("dither_scale", IIO_SEPARATE,
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&ad5766_dither_scale_enum),
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{}
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};
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#define AD576x_CHANNEL(_chan, _bits) { \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.output = 1, \
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.channel = (_chan), \
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.address = (_chan), \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | \
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BIT(IIO_CHAN_INFO_SCALE), \
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.scan_index = (_chan), \
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.scan_type = { \
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.sign = 'u', \
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.realbits = (_bits), \
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.storagebits = 16, \
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.shift = 16 - (_bits), \
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}, \
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.ext_info = ad5766_ext_info, \
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}
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#define DECLARE_AD576x_CHANNELS(_name, _bits) \
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const struct iio_chan_spec _name[] = { \
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AD576x_CHANNEL(0, (_bits)), \
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AD576x_CHANNEL(1, (_bits)), \
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AD576x_CHANNEL(2, (_bits)), \
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AD576x_CHANNEL(3, (_bits)), \
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AD576x_CHANNEL(4, (_bits)), \
|
|
AD576x_CHANNEL(5, (_bits)), \
|
|
AD576x_CHANNEL(6, (_bits)), \
|
|
AD576x_CHANNEL(7, (_bits)), \
|
|
AD576x_CHANNEL(8, (_bits)), \
|
|
AD576x_CHANNEL(9, (_bits)), \
|
|
AD576x_CHANNEL(10, (_bits)), \
|
|
AD576x_CHANNEL(11, (_bits)), \
|
|
AD576x_CHANNEL(12, (_bits)), \
|
|
AD576x_CHANNEL(13, (_bits)), \
|
|
AD576x_CHANNEL(14, (_bits)), \
|
|
AD576x_CHANNEL(15, (_bits)), \
|
|
}
|
|
|
|
static DECLARE_AD576x_CHANNELS(ad5766_channels, 16);
|
|
static DECLARE_AD576x_CHANNELS(ad5767_channels, 12);
|
|
|
|
static const struct ad5766_chip_info ad5766_chip_infos[] = {
|
|
[ID_AD5766] = {
|
|
.num_channels = ARRAY_SIZE(ad5766_channels),
|
|
.channels = ad5766_channels,
|
|
},
|
|
[ID_AD5767] = {
|
|
.num_channels = ARRAY_SIZE(ad5767_channels),
|
|
.channels = ad5767_channels,
|
|
},
|
|
};
|
|
|
|
static int ad5766_get_output_range(struct ad5766_state *st)
|
|
{
|
|
int i, ret, min, max, tmp[2];
|
|
|
|
ret = device_property_read_u32_array(&st->spi->dev,
|
|
"output-range-microvolts",
|
|
tmp, 2);
|
|
if (ret)
|
|
return ret;
|
|
|
|
min = tmp[0] / 1000000;
|
|
max = tmp[1] / 1000000;
|
|
for (i = 0; i < ARRAY_SIZE(ad5766_span_tbl); i++) {
|
|
if (ad5766_span_tbl[i].min != min ||
|
|
ad5766_span_tbl[i].max != max)
|
|
continue;
|
|
|
|
st->crt_range = i;
|
|
|
|
return 0;
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int ad5766_default_setup(struct ad5766_state *st)
|
|
{
|
|
uint16_t val;
|
|
int ret, i;
|
|
|
|
/* Always issue a reset before writing to the span register. */
|
|
ret = ad5766_reset(st);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = ad5766_get_output_range(st);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Dither power down */
|
|
st->dither_enable = GENMASK(15, 0);
|
|
ret = __ad5766_spi_write(st, AD5766_CMD_WR_PWR_DITHER,
|
|
st->dither_enable);
|
|
if (ret)
|
|
return ret;
|
|
|
|
st->dither_source = 0;
|
|
for (i = 0; i < ARRAY_SIZE(ad5766_channels); i++)
|
|
st->dither_source |= AD5766_DITHER_SOURCE(i, 0);
|
|
val = FIELD_GET(AD5766_LOWER_WORD_SPI_MASK, st->dither_source);
|
|
ret = __ad5766_spi_write(st, AD5766_CMD_DITHER_SIG_1, val);
|
|
if (ret)
|
|
return ret;
|
|
|
|
val = FIELD_GET(AD5766_UPPER_WORD_SPI_MASK, st->dither_source);
|
|
ret = __ad5766_spi_write(st, AD5766_CMD_DITHER_SIG_2, val);
|
|
if (ret)
|
|
return ret;
|
|
|
|
st->dither_scale = 0;
|
|
val = FIELD_GET(AD5766_LOWER_WORD_SPI_MASK, st->dither_scale);
|
|
ret = __ad5766_spi_write(st, AD5766_CMD_DITHER_SCALE_1, val);
|
|
if (ret)
|
|
return ret;
|
|
|
|
val = FIELD_GET(AD5766_UPPER_WORD_SPI_MASK, st->dither_scale);
|
|
ret = __ad5766_spi_write(st, AD5766_CMD_DITHER_SCALE_2, val);
|
|
if (ret)
|
|
return ret;
|
|
|
|
st->dither_invert = 0;
|
|
ret = __ad5766_spi_write(st, AD5766_CMD_INV_DITHER, st->dither_invert);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return __ad5766_spi_write(st, AD5766_CMD_SPAN_REG, st->crt_range);
|
|
}
|
|
|
|
static irqreturn_t ad5766_trigger_handler(int irq, void *p)
|
|
{
|
|
struct iio_poll_func *pf = p;
|
|
struct iio_dev *indio_dev = pf->indio_dev;
|
|
struct iio_buffer *buffer = indio_dev->buffer;
|
|
struct ad5766_state *st = iio_priv(indio_dev);
|
|
int ret, ch, i;
|
|
u16 data[ARRAY_SIZE(ad5766_channels)];
|
|
|
|
ret = iio_pop_from_buffer(buffer, data);
|
|
if (ret)
|
|
goto done;
|
|
|
|
i = 0;
|
|
mutex_lock(&st->lock);
|
|
for_each_set_bit(ch, indio_dev->active_scan_mask,
|
|
st->chip_info->num_channels - 1)
|
|
__ad5766_spi_write(st, AD5766_CMD_WR_IN_REG(ch), data[i++]);
|
|
|
|
__ad5766_spi_write(st, AD5766_CMD_SW_LDAC,
|
|
*indio_dev->active_scan_mask);
|
|
mutex_unlock(&st->lock);
|
|
|
|
done:
|
|
iio_trigger_notify_done(indio_dev->trig);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int ad5766_probe(struct spi_device *spi)
|
|
{
|
|
enum ad5766_type type;
|
|
struct iio_dev *indio_dev;
|
|
struct ad5766_state *st;
|
|
int ret;
|
|
|
|
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
|
|
if (!indio_dev)
|
|
return -ENOMEM;
|
|
|
|
st = iio_priv(indio_dev);
|
|
mutex_init(&st->lock);
|
|
|
|
st->spi = spi;
|
|
type = spi_get_device_id(spi)->driver_data;
|
|
st->chip_info = &ad5766_chip_infos[type];
|
|
|
|
indio_dev->channels = st->chip_info->channels;
|
|
indio_dev->num_channels = st->chip_info->num_channels;
|
|
indio_dev->info = &ad5766_info;
|
|
indio_dev->name = spi_get_device_id(spi)->name;
|
|
indio_dev->modes = INDIO_DIRECT_MODE;
|
|
|
|
st->gpio_reset = devm_gpiod_get_optional(&st->spi->dev, "reset",
|
|
GPIOD_OUT_LOW);
|
|
if (IS_ERR(st->gpio_reset))
|
|
return PTR_ERR(st->gpio_reset);
|
|
|
|
ret = ad5766_default_setup(st);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Configure trigger buffer */
|
|
ret = devm_iio_triggered_buffer_setup_ext(&spi->dev, indio_dev, NULL,
|
|
ad5766_trigger_handler,
|
|
IIO_BUFFER_DIRECTION_OUT,
|
|
NULL,
|
|
NULL);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return devm_iio_device_register(&spi->dev, indio_dev);
|
|
}
|
|
|
|
static const struct of_device_id ad5766_dt_match[] = {
|
|
{ .compatible = "adi,ad5766" },
|
|
{ .compatible = "adi,ad5767" },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, ad5766_dt_match);
|
|
|
|
static const struct spi_device_id ad5766_spi_ids[] = {
|
|
{ "ad5766", ID_AD5766 },
|
|
{ "ad5767", ID_AD5767 },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(spi, ad5766_spi_ids);
|
|
|
|
static struct spi_driver ad5766_driver = {
|
|
.driver = {
|
|
.name = "ad5766",
|
|
.of_match_table = ad5766_dt_match,
|
|
},
|
|
.probe = ad5766_probe,
|
|
.id_table = ad5766_spi_ids,
|
|
};
|
|
module_spi_driver(ad5766_driver);
|
|
|
|
MODULE_AUTHOR("Denis-Gabriel Gheorghescu <denis.gheorghescu@analog.com>");
|
|
MODULE_DESCRIPTION("Analog Devices AD5766/AD5767 DACs");
|
|
MODULE_LICENSE("GPL v2");
|