143 lines
4.0 KiB
C
143 lines
4.0 KiB
C
// SPDX-License-Identifier: MIT
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#include <drm/drm_crtc.h>
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#include "crc.h"
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#include "core.h"
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#include "disp.h"
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#include "head.h"
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#include <nvif/push507c.h>
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#include <nvhw/class/cl907d.h>
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#define CRC907D_MAX_ENTRIES 255
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struct crc907d_notifier {
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u32 status;
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u32 :32; /* reserved */
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struct crc907d_entry {
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u32 status;
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u32 compositor_crc;
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u32 output_crc[2];
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} entries[CRC907D_MAX_ENTRIES];
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} __packed;
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static int
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crc907d_set_src(struct nv50_head *head, int or, enum nv50_crc_source_type source,
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struct nv50_crc_notifier_ctx *ctx)
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{
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struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
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const int i = head->base.index;
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u32 crc_args = NVDEF(NV907D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, CORE) |
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NVDEF(NV907D, HEAD_SET_CRC_CONTROL, EXPECT_BUFFER_COLLAPSE, FALSE) |
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NVDEF(NV907D, HEAD_SET_CRC_CONTROL, TIMESTAMP_MODE, FALSE) |
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NVDEF(NV907D, HEAD_SET_CRC_CONTROL, SECONDARY_OUTPUT, NONE) |
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NVDEF(NV907D, HEAD_SET_CRC_CONTROL, CRC_DURING_SNOOZE, DISABLE) |
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NVDEF(NV907D, HEAD_SET_CRC_CONTROL, WIDE_PIPE_CRC, ENABLE);
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int ret;
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switch (source) {
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case NV50_CRC_SOURCE_TYPE_SOR:
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crc_args |= NVDEF(NV907D, HEAD_SET_CRC_CONTROL, PRIMARY_OUTPUT, SOR(or));
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break;
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case NV50_CRC_SOURCE_TYPE_PIOR:
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crc_args |= NVDEF(NV907D, HEAD_SET_CRC_CONTROL, PRIMARY_OUTPUT, PIOR(or));
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break;
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case NV50_CRC_SOURCE_TYPE_DAC:
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crc_args |= NVDEF(NV907D, HEAD_SET_CRC_CONTROL, PRIMARY_OUTPUT, DAC(or));
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break;
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case NV50_CRC_SOURCE_TYPE_RG:
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crc_args |= NVDEF(NV907D, HEAD_SET_CRC_CONTROL, PRIMARY_OUTPUT, RG(i));
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break;
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case NV50_CRC_SOURCE_TYPE_SF:
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crc_args |= NVDEF(NV907D, HEAD_SET_CRC_CONTROL, PRIMARY_OUTPUT, SF(i));
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break;
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case NV50_CRC_SOURCE_NONE:
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crc_args |= NVDEF(NV907D, HEAD_SET_CRC_CONTROL, PRIMARY_OUTPUT, NONE);
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break;
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}
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if ((ret = PUSH_WAIT(push, 4)))
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return ret;
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if (source) {
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PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx->ntfy.handle);
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PUSH_MTHD(push, NV907D, HEAD_SET_CRC_CONTROL(i), crc_args);
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} else {
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PUSH_MTHD(push, NV907D, HEAD_SET_CRC_CONTROL(i), crc_args);
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PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CRC(i), 0);
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}
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return 0;
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}
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static int
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crc907d_set_ctx(struct nv50_head *head, struct nv50_crc_notifier_ctx *ctx)
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{
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struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
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const int i = head->base.index;
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int ret;
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if ((ret = PUSH_WAIT(push, 2)))
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return ret;
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PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx ? ctx->ntfy.handle : 0);
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return 0;
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}
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static u32 crc907d_get_entry(struct nv50_head *head,
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struct nv50_crc_notifier_ctx *ctx,
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enum nv50_crc_source source, int idx)
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{
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struct crc907d_notifier __iomem *notifier = ctx->mem.object.map.ptr;
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return ioread32_native(¬ifier->entries[idx].output_crc[0]);
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}
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static bool crc907d_ctx_finished(struct nv50_head *head,
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struct nv50_crc_notifier_ctx *ctx)
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{
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struct nouveau_drm *drm = nouveau_drm(head->base.base.dev);
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struct crc907d_notifier __iomem *notifier = ctx->mem.object.map.ptr;
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const u32 status = ioread32_native(¬ifier->status);
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const u32 overflow = status & 0x0000003e;
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if (!(status & 0x00000001))
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return false;
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if (overflow) {
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const char *engine = NULL;
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switch (overflow) {
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case 0x00000004: engine = "DSI"; break;
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case 0x00000008: engine = "Compositor"; break;
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case 0x00000010: engine = "CRC output 1"; break;
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case 0x00000020: engine = "CRC output 2"; break;
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}
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if (engine)
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NV_ERROR(drm,
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"CRC notifier context for head %d overflowed on %s: %x\n",
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head->base.index, engine, status);
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else
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NV_ERROR(drm,
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"CRC notifier context for head %d overflowed: %x\n",
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head->base.index, status);
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}
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NV_DEBUG(drm, "Head %d CRC context status: %x\n",
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head->base.index, status);
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return true;
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}
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const struct nv50_crc_func crc907d = {
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.set_src = crc907d_set_src,
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.set_ctx = crc907d_set_ctx,
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.get_entry = crc907d_get_entry,
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.ctx_finished = crc907d_ctx_finished,
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.flip_threshold = CRC907D_MAX_ENTRIES - 10,
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.num_entries = CRC907D_MAX_ENTRIES,
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.notifier_len = sizeof(struct crc907d_notifier),
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};
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