994 lines
23 KiB
C
994 lines
23 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/delay.h>
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#include "mgag200_drv.h"
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/*
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* G200
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*/
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static int mgag200_pixpll_compute_g200(struct mgag200_pll *pixpll, long clock,
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struct mgag200_pll_values *pixpllc)
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{
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struct mga_device *mdev = pixpll->mdev;
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struct drm_device *dev = &mdev->base;
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const int post_div_max = 7;
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const int in_div_min = 1;
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const int in_div_max = 6;
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const int feed_div_min = 7;
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const int feed_div_max = 127;
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u8 testp, testm, testn;
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u8 n = 0, m = 0, p, s;
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long f_vco;
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long computed;
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long delta, tmp_delta;
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long ref_clk = mdev->model.g200.ref_clk;
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long p_clk_min = mdev->model.g200.pclk_min;
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long p_clk_max = mdev->model.g200.pclk_max;
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if (clock > p_clk_max) {
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drm_err(dev, "Pixel Clock %ld too high\n", clock);
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return -EINVAL;
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}
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if (clock < p_clk_min >> 3)
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clock = p_clk_min >> 3;
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f_vco = clock;
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for (testp = 0;
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testp <= post_div_max && f_vco < p_clk_min;
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testp = (testp << 1) + 1, f_vco <<= 1)
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;
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p = testp + 1;
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delta = clock;
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for (testm = in_div_min; testm <= in_div_max; testm++) {
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for (testn = feed_div_min; testn <= feed_div_max; testn++) {
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computed = ref_clk * (testn + 1) / (testm + 1);
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if (computed < f_vco)
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tmp_delta = f_vco - computed;
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else
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tmp_delta = computed - f_vco;
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if (tmp_delta < delta) {
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delta = tmp_delta;
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m = testm + 1;
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n = testn + 1;
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}
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}
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}
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f_vco = ref_clk * n / m;
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if (f_vco < 100000)
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s = 0;
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else if (f_vco < 140000)
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s = 1;
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else if (f_vco < 180000)
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s = 2;
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else
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s = 3;
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drm_dbg_kms(dev, "clock: %ld vco: %ld m: %d n: %d p: %d s: %d\n",
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clock, f_vco, m, n, p, s);
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pixpllc->m = m;
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pixpllc->n = n;
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pixpllc->p = p;
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pixpllc->s = s;
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return 0;
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}
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static void
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mgag200_pixpll_update_g200(struct mgag200_pll *pixpll, const struct mgag200_pll_values *pixpllc)
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{
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struct mga_device *mdev = pixpll->mdev;
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unsigned int pixpllcm, pixpllcn, pixpllcp, pixpllcs;
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u8 xpixpllcm, xpixpllcn, xpixpllcp;
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pixpllcm = pixpllc->m - 1;
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pixpllcn = pixpllc->n - 1;
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pixpllcp = pixpllc->p - 1;
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pixpllcs = pixpllc->s;
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xpixpllcm = pixpllcm;
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xpixpllcn = pixpllcn;
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xpixpllcp = (pixpllcs << 3) | pixpllcp;
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WREG_MISC_MASKED(MGAREG_MISC_CLKSEL_MGA, MGAREG_MISC_CLKSEL_MASK);
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WREG_DAC(MGA1064_PIX_PLLC_M, xpixpllcm);
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WREG_DAC(MGA1064_PIX_PLLC_N, xpixpllcn);
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WREG_DAC(MGA1064_PIX_PLLC_P, xpixpllcp);
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}
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static const struct mgag200_pll_funcs mgag200_pixpll_funcs_g200 = {
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.compute = mgag200_pixpll_compute_g200,
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.update = mgag200_pixpll_update_g200,
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};
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/*
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* G200SE
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*/
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static int mgag200_pixpll_compute_g200se_00(struct mgag200_pll *pixpll, long clock,
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struct mgag200_pll_values *pixpllc)
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{
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static const unsigned int vcomax = 320000;
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static const unsigned int vcomin = 160000;
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static const unsigned int pllreffreq = 25000;
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unsigned int delta, tmpdelta, permitteddelta;
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unsigned int testp, testm, testn;
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unsigned int p, m, n, s;
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unsigned int computed;
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m = n = p = s = 0;
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delta = 0xffffffff;
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permitteddelta = clock * 5 / 1000;
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for (testp = 8; testp > 0; testp /= 2) {
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if (clock * testp > vcomax)
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continue;
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if (clock * testp < vcomin)
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continue;
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for (testn = 17; testn < 256; testn++) {
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for (testm = 1; testm < 32; testm++) {
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computed = (pllreffreq * testn) / (testm * testp);
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if (computed > clock)
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tmpdelta = computed - clock;
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else
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tmpdelta = clock - computed;
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if (tmpdelta < delta) {
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delta = tmpdelta;
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m = testm;
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n = testn;
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p = testp;
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}
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}
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}
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}
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if (delta > permitteddelta) {
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pr_warn("PLL delta too large\n");
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return -EINVAL;
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}
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pixpllc->m = m;
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pixpllc->n = n;
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pixpllc->p = p;
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pixpllc->s = s;
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return 0;
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}
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static void mgag200_pixpll_update_g200se_00(struct mgag200_pll *pixpll,
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const struct mgag200_pll_values *pixpllc)
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{
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unsigned int pixpllcm, pixpllcn, pixpllcp, pixpllcs;
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u8 xpixpllcm, xpixpllcn, xpixpllcp;
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struct mga_device *mdev = pixpll->mdev;
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pixpllcm = pixpllc->m - 1;
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pixpllcn = pixpllc->n - 1;
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pixpllcp = pixpllc->p - 1;
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pixpllcs = pixpllc->s;
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xpixpllcm = pixpllcm | ((pixpllcn & BIT(8)) >> 1);
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xpixpllcn = pixpllcn;
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xpixpllcp = (pixpllcs << 3) | pixpllcp;
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WREG_MISC_MASKED(MGAREG_MISC_CLKSEL_MGA, MGAREG_MISC_CLKSEL_MASK);
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WREG_DAC(MGA1064_PIX_PLLC_M, xpixpllcm);
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WREG_DAC(MGA1064_PIX_PLLC_N, xpixpllcn);
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WREG_DAC(MGA1064_PIX_PLLC_P, xpixpllcp);
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}
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static int mgag200_pixpll_compute_g200se_04(struct mgag200_pll *pixpll, long clock,
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struct mgag200_pll_values *pixpllc)
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{
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static const unsigned int vcomax = 1600000;
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static const unsigned int vcomin = 800000;
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static const unsigned int pllreffreq = 25000;
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static const unsigned int pvalues_e4[] = {16, 14, 12, 10, 8, 6, 4, 2, 1};
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unsigned int delta, tmpdelta, permitteddelta;
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unsigned int testp, testm, testn;
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unsigned int p, m, n, s;
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unsigned int computed;
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unsigned int fvv;
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unsigned int i;
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m = n = p = s = 0;
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delta = 0xffffffff;
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if (clock < 25000)
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clock = 25000;
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clock = clock * 2;
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/* Permited delta is 0.5% as VESA Specification */
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permitteddelta = clock * 5 / 1000;
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for (i = 0 ; i < ARRAY_SIZE(pvalues_e4); i++) {
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testp = pvalues_e4[i];
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if ((clock * testp) > vcomax)
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continue;
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if ((clock * testp) < vcomin)
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continue;
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for (testn = 50; testn <= 256; testn++) {
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for (testm = 1; testm <= 32; testm++) {
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computed = (pllreffreq * testn) / (testm * testp);
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if (computed > clock)
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tmpdelta = computed - clock;
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else
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tmpdelta = clock - computed;
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if (tmpdelta < delta) {
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delta = tmpdelta;
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m = testm;
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n = testn;
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p = testp;
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}
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}
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}
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}
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fvv = pllreffreq * n / m;
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fvv = (fvv - 800000) / 50000;
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if (fvv > 15)
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fvv = 15;
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s = fvv << 1;
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if (delta > permitteddelta) {
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pr_warn("PLL delta too large\n");
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return -EINVAL;
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}
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pixpllc->m = m;
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pixpllc->n = n;
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pixpllc->p = p;
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pixpllc->s = s;
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return 0;
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}
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static void mgag200_pixpll_update_g200se_04(struct mgag200_pll *pixpll,
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const struct mgag200_pll_values *pixpllc)
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{
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unsigned int pixpllcm, pixpllcn, pixpllcp, pixpllcs;
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u8 xpixpllcm, xpixpllcn, xpixpllcp;
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struct mga_device *mdev = pixpll->mdev;
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pixpllcm = pixpllc->m - 1;
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pixpllcn = pixpllc->n - 1;
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pixpllcp = pixpllc->p - 1;
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pixpllcs = pixpllc->s;
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xpixpllcm = pixpllcm | ((pixpllcn & BIT(8)) >> 1);
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xpixpllcn = pixpllcn;
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xpixpllcp = (pixpllcs << 3) | pixpllcp;
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WREG_MISC_MASKED(MGAREG_MISC_CLKSEL_MGA, MGAREG_MISC_CLKSEL_MASK);
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WREG_DAC(MGA1064_PIX_PLLC_M, xpixpllcm);
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WREG_DAC(MGA1064_PIX_PLLC_N, xpixpllcn);
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WREG_DAC(MGA1064_PIX_PLLC_P, xpixpllcp);
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WREG_DAC(0x1a, 0x09);
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msleep(20);
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WREG_DAC(0x1a, 0x01);
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}
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static const struct mgag200_pll_funcs mgag200_pixpll_funcs_g200se_00 = {
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.compute = mgag200_pixpll_compute_g200se_00,
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.update = mgag200_pixpll_update_g200se_00,
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};
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static const struct mgag200_pll_funcs mgag200_pixpll_funcs_g200se_04 = {
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.compute = mgag200_pixpll_compute_g200se_04,
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.update = mgag200_pixpll_update_g200se_04,
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};
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/*
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* G200WB
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*/
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static int mgag200_pixpll_compute_g200wb(struct mgag200_pll *pixpll, long clock,
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struct mgag200_pll_values *pixpllc)
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{
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static const unsigned int vcomax = 550000;
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static const unsigned int vcomin = 150000;
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static const unsigned int pllreffreq = 48000;
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unsigned int delta, tmpdelta;
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unsigned int testp, testm, testn;
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unsigned int p, m, n, s;
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unsigned int computed;
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m = n = p = s = 0;
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delta = 0xffffffff;
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for (testp = 1; testp < 9; testp++) {
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if (clock * testp > vcomax)
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continue;
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if (clock * testp < vcomin)
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continue;
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for (testm = 1; testm < 17; testm++) {
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for (testn = 1; testn < 151; testn++) {
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computed = (pllreffreq * testn) / (testm * testp);
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if (computed > clock)
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tmpdelta = computed - clock;
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else
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tmpdelta = clock - computed;
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if (tmpdelta < delta) {
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delta = tmpdelta;
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n = testn;
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m = testm;
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p = testp;
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s = 0;
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}
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}
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}
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}
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pixpllc->m = m;
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pixpllc->n = n;
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pixpllc->p = p;
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pixpllc->s = s;
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return 0;
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}
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static void
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mgag200_pixpll_update_g200wb(struct mgag200_pll *pixpll, const struct mgag200_pll_values *pixpllc)
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{
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unsigned int pixpllcm, pixpllcn, pixpllcp, pixpllcs;
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u8 xpixpllcm, xpixpllcn, xpixpllcp, tmp;
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int i, j, tmpcount, vcount;
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struct mga_device *mdev = pixpll->mdev;
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bool pll_locked = false;
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pixpllcm = pixpllc->m - 1;
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pixpllcn = pixpllc->n - 1;
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pixpllcp = pixpllc->p - 1;
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pixpllcs = pixpllc->s;
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xpixpllcm = ((pixpllcn & BIT(8)) >> 1) | pixpllcm;
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xpixpllcn = pixpllcn;
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xpixpllcp = ((pixpllcn & GENMASK(10, 9)) >> 3) | (pixpllcs << 3) | pixpllcp;
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WREG_MISC_MASKED(MGAREG_MISC_CLKSEL_MGA, MGAREG_MISC_CLKSEL_MASK);
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for (i = 0; i <= 32 && pll_locked == false; i++) {
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if (i > 0) {
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WREG8(MGAREG_CRTC_INDEX, 0x1e);
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tmp = RREG8(MGAREG_CRTC_DATA);
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if (tmp < 0xff)
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WREG8(MGAREG_CRTC_DATA, tmp+1);
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}
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/* set pixclkdis to 1 */
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WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
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tmp = RREG8(DAC_DATA);
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tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
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WREG8(DAC_DATA, tmp);
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WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
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tmp = RREG8(DAC_DATA);
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tmp |= MGA1064_REMHEADCTL_CLKDIS;
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WREG8(DAC_DATA, tmp);
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/* select PLL Set C */
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tmp = RREG8(MGAREG_MEM_MISC_READ);
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tmp |= 0x3 << 2;
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WREG8(MGAREG_MEM_MISC_WRITE, tmp);
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WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
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tmp = RREG8(DAC_DATA);
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tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80;
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WREG8(DAC_DATA, tmp);
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udelay(500);
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/* reset the PLL */
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WREG8(DAC_INDEX, MGA1064_VREF_CTL);
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tmp = RREG8(DAC_DATA);
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tmp &= ~0x04;
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WREG8(DAC_DATA, tmp);
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udelay(50);
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/* program pixel pll register */
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WREG_DAC(MGA1064_WB_PIX_PLLC_N, xpixpllcn);
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WREG_DAC(MGA1064_WB_PIX_PLLC_M, xpixpllcm);
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WREG_DAC(MGA1064_WB_PIX_PLLC_P, xpixpllcp);
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udelay(50);
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/* turn pll on */
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WREG8(DAC_INDEX, MGA1064_VREF_CTL);
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tmp = RREG8(DAC_DATA);
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tmp |= 0x04;
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WREG_DAC(MGA1064_VREF_CTL, tmp);
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udelay(500);
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/* select the pixel pll */
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WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
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tmp = RREG8(DAC_DATA);
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tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
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tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
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WREG8(DAC_DATA, tmp);
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WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
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tmp = RREG8(DAC_DATA);
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tmp &= ~MGA1064_REMHEADCTL_CLKSL_MSK;
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tmp |= MGA1064_REMHEADCTL_CLKSL_PLL;
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WREG8(DAC_DATA, tmp);
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/* reset dotclock rate bit */
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WREG8(MGAREG_SEQ_INDEX, 1);
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tmp = RREG8(MGAREG_SEQ_DATA);
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tmp &= ~0x8;
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WREG8(MGAREG_SEQ_DATA, tmp);
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WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
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tmp = RREG8(DAC_DATA);
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tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
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WREG8(DAC_DATA, tmp);
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vcount = RREG8(MGAREG_VCOUNT);
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for (j = 0; j < 30 && pll_locked == false; j++) {
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tmpcount = RREG8(MGAREG_VCOUNT);
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if (tmpcount < vcount)
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vcount = 0;
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if ((tmpcount - vcount) > 2)
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pll_locked = true;
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else
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udelay(5);
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}
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}
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WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
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tmp = RREG8(DAC_DATA);
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tmp &= ~MGA1064_REMHEADCTL_CLKDIS;
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WREG_DAC(MGA1064_REMHEADCTL, tmp);
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}
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static const struct mgag200_pll_funcs mgag200_pixpll_funcs_g200wb = {
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.compute = mgag200_pixpll_compute_g200wb,
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.update = mgag200_pixpll_update_g200wb,
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};
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/*
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* G200EV
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*/
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static int mgag200_pixpll_compute_g200ev(struct mgag200_pll *pixpll, long clock,
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struct mgag200_pll_values *pixpllc)
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{
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static const unsigned int vcomax = 550000;
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static const unsigned int vcomin = 150000;
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static const unsigned int pllreffreq = 50000;
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unsigned int delta, tmpdelta;
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unsigned int testp, testm, testn;
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unsigned int p, m, n, s;
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unsigned int computed;
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m = n = p = s = 0;
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delta = 0xffffffff;
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for (testp = 16; testp > 0; testp--) {
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if (clock * testp > vcomax)
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continue;
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if (clock * testp < vcomin)
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continue;
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for (testn = 1; testn < 257; testn++) {
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for (testm = 1; testm < 17; testm++) {
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computed = (pllreffreq * testn) /
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(testm * testp);
|
|
if (computed > clock)
|
|
tmpdelta = computed - clock;
|
|
else
|
|
tmpdelta = clock - computed;
|
|
if (tmpdelta < delta) {
|
|
delta = tmpdelta;
|
|
n = testn;
|
|
m = testm;
|
|
p = testp;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
pixpllc->m = m;
|
|
pixpllc->n = n;
|
|
pixpllc->p = p;
|
|
pixpllc->s = s;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
mgag200_pixpll_update_g200ev(struct mgag200_pll *pixpll, const struct mgag200_pll_values *pixpllc)
|
|
{
|
|
unsigned int pixpllcm, pixpllcn, pixpllcp, pixpllcs;
|
|
u8 xpixpllcm, xpixpllcn, xpixpllcp, tmp;
|
|
struct mga_device *mdev = pixpll->mdev;
|
|
|
|
pixpllcm = pixpllc->m - 1;
|
|
pixpllcn = pixpllc->n - 1;
|
|
pixpllcp = pixpllc->p - 1;
|
|
pixpllcs = pixpllc->s;
|
|
|
|
xpixpllcm = pixpllcm;
|
|
xpixpllcn = pixpllcn;
|
|
xpixpllcp = (pixpllcs << 3) | pixpllcp;
|
|
|
|
WREG_MISC_MASKED(MGAREG_MISC_CLKSEL_MGA, MGAREG_MISC_CLKSEL_MASK);
|
|
|
|
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
|
tmp = RREG8(DAC_DATA);
|
|
tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
|
|
WREG8(DAC_DATA, tmp);
|
|
|
|
tmp = RREG8(MGAREG_MEM_MISC_READ);
|
|
tmp |= 0x3 << 2;
|
|
WREG8(MGAREG_MEM_MISC_WRITE, tmp);
|
|
|
|
WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
|
|
tmp = RREG8(DAC_DATA);
|
|
WREG8(DAC_DATA, tmp & ~0x40);
|
|
|
|
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
|
tmp = RREG8(DAC_DATA);
|
|
tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
|
|
WREG8(DAC_DATA, tmp);
|
|
|
|
WREG_DAC(MGA1064_EV_PIX_PLLC_M, xpixpllcm);
|
|
WREG_DAC(MGA1064_EV_PIX_PLLC_N, xpixpllcn);
|
|
WREG_DAC(MGA1064_EV_PIX_PLLC_P, xpixpllcp);
|
|
|
|
udelay(50);
|
|
|
|
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
|
tmp = RREG8(DAC_DATA);
|
|
tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
|
|
WREG8(DAC_DATA, tmp);
|
|
|
|
udelay(500);
|
|
|
|
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
|
tmp = RREG8(DAC_DATA);
|
|
tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
|
|
tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
|
|
WREG8(DAC_DATA, tmp);
|
|
|
|
WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
|
|
tmp = RREG8(DAC_DATA);
|
|
WREG8(DAC_DATA, tmp | 0x40);
|
|
|
|
tmp = RREG8(MGAREG_MEM_MISC_READ);
|
|
tmp |= (0x3 << 2);
|
|
WREG8(MGAREG_MEM_MISC_WRITE, tmp);
|
|
|
|
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
|
tmp = RREG8(DAC_DATA);
|
|
tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
|
|
WREG8(DAC_DATA, tmp);
|
|
}
|
|
|
|
static const struct mgag200_pll_funcs mgag200_pixpll_funcs_g200ev = {
|
|
.compute = mgag200_pixpll_compute_g200ev,
|
|
.update = mgag200_pixpll_update_g200ev,
|
|
};
|
|
|
|
/*
|
|
* G200EH
|
|
*/
|
|
|
|
static int mgag200_pixpll_compute_g200eh(struct mgag200_pll *pixpll, long clock,
|
|
struct mgag200_pll_values *pixpllc)
|
|
{
|
|
static const unsigned int vcomax = 800000;
|
|
static const unsigned int vcomin = 400000;
|
|
static const unsigned int pllreffreq = 33333;
|
|
|
|
unsigned int delta, tmpdelta;
|
|
unsigned int testp, testm, testn;
|
|
unsigned int p, m, n, s;
|
|
unsigned int computed;
|
|
|
|
m = n = p = s = 0;
|
|
delta = 0xffffffff;
|
|
|
|
for (testp = 16; testp > 0; testp >>= 1) {
|
|
if (clock * testp > vcomax)
|
|
continue;
|
|
if (clock * testp < vcomin)
|
|
continue;
|
|
|
|
for (testm = 1; testm < 33; testm++) {
|
|
for (testn = 17; testn < 257; testn++) {
|
|
computed = (pllreffreq * testn) / (testm * testp);
|
|
if (computed > clock)
|
|
tmpdelta = computed - clock;
|
|
else
|
|
tmpdelta = clock - computed;
|
|
if (tmpdelta < delta) {
|
|
delta = tmpdelta;
|
|
n = testn;
|
|
m = testm;
|
|
p = testp;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
pixpllc->m = m;
|
|
pixpllc->n = n;
|
|
pixpllc->p = p;
|
|
pixpllc->s = s;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
mgag200_pixpll_update_g200eh(struct mgag200_pll *pixpll, const struct mgag200_pll_values *pixpllc)
|
|
{
|
|
unsigned int pixpllcm, pixpllcn, pixpllcp, pixpllcs;
|
|
u8 xpixpllcm, xpixpllcn, xpixpllcp, tmp;
|
|
int i, j, tmpcount, vcount;
|
|
struct mga_device *mdev = pixpll->mdev;
|
|
bool pll_locked = false;
|
|
|
|
pixpllcm = pixpllc->m - 1;
|
|
pixpllcn = pixpllc->n - 1;
|
|
pixpllcp = pixpllc->p - 1;
|
|
pixpllcs = pixpllc->s;
|
|
|
|
xpixpllcm = ((pixpllcn & BIT(8)) >> 1) | pixpllcm;
|
|
xpixpllcn = pixpllcn;
|
|
xpixpllcp = (pixpllcs << 3) | pixpllcp;
|
|
|
|
WREG_MISC_MASKED(MGAREG_MISC_CLKSEL_MGA, MGAREG_MISC_CLKSEL_MASK);
|
|
|
|
for (i = 0; i <= 32 && pll_locked == false; i++) {
|
|
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
|
tmp = RREG8(DAC_DATA);
|
|
tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
|
|
WREG8(DAC_DATA, tmp);
|
|
|
|
tmp = RREG8(MGAREG_MEM_MISC_READ);
|
|
tmp |= 0x3 << 2;
|
|
WREG8(MGAREG_MEM_MISC_WRITE, tmp);
|
|
|
|
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
|
tmp = RREG8(DAC_DATA);
|
|
tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
|
|
WREG8(DAC_DATA, tmp);
|
|
|
|
udelay(500);
|
|
|
|
WREG_DAC(MGA1064_EH_PIX_PLLC_M, xpixpllcm);
|
|
WREG_DAC(MGA1064_EH_PIX_PLLC_N, xpixpllcn);
|
|
WREG_DAC(MGA1064_EH_PIX_PLLC_P, xpixpllcp);
|
|
|
|
udelay(500);
|
|
|
|
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
|
tmp = RREG8(DAC_DATA);
|
|
tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
|
|
tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
|
|
WREG8(DAC_DATA, tmp);
|
|
|
|
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
|
tmp = RREG8(DAC_DATA);
|
|
tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
|
|
tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
|
|
WREG8(DAC_DATA, tmp);
|
|
|
|
vcount = RREG8(MGAREG_VCOUNT);
|
|
|
|
for (j = 0; j < 30 && pll_locked == false; j++) {
|
|
tmpcount = RREG8(MGAREG_VCOUNT);
|
|
if (tmpcount < vcount)
|
|
vcount = 0;
|
|
if ((tmpcount - vcount) > 2)
|
|
pll_locked = true;
|
|
else
|
|
udelay(5);
|
|
}
|
|
}
|
|
}
|
|
|
|
static const struct mgag200_pll_funcs mgag200_pixpll_funcs_g200eh = {
|
|
.compute = mgag200_pixpll_compute_g200eh,
|
|
.update = mgag200_pixpll_update_g200eh,
|
|
};
|
|
|
|
/*
|
|
* G200EH3
|
|
*/
|
|
|
|
static int mgag200_pixpll_compute_g200eh3(struct mgag200_pll *pixpll, long clock,
|
|
struct mgag200_pll_values *pixpllc)
|
|
{
|
|
static const unsigned int vcomax = 3000000;
|
|
static const unsigned int vcomin = 1500000;
|
|
static const unsigned int pllreffreq = 25000;
|
|
|
|
unsigned int delta, tmpdelta;
|
|
unsigned int testp, testm, testn;
|
|
unsigned int p, m, n, s;
|
|
unsigned int computed;
|
|
|
|
m = n = p = s = 0;
|
|
delta = 0xffffffff;
|
|
testp = 0;
|
|
|
|
for (testm = 150; testm >= 6; testm--) {
|
|
if (clock * testm > vcomax)
|
|
continue;
|
|
if (clock * testm < vcomin)
|
|
continue;
|
|
for (testn = 120; testn >= 60; testn--) {
|
|
computed = (pllreffreq * testn) / testm;
|
|
if (computed > clock)
|
|
tmpdelta = computed - clock;
|
|
else
|
|
tmpdelta = clock - computed;
|
|
if (tmpdelta < delta) {
|
|
delta = tmpdelta;
|
|
n = testn + 1;
|
|
m = testm + 1;
|
|
p = testp + 1;
|
|
}
|
|
if (delta == 0)
|
|
break;
|
|
}
|
|
if (delta == 0)
|
|
break;
|
|
}
|
|
|
|
pixpllc->m = m;
|
|
pixpllc->n = n;
|
|
pixpllc->p = p;
|
|
pixpllc->s = s;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct mgag200_pll_funcs mgag200_pixpll_funcs_g200eh3 = {
|
|
.compute = mgag200_pixpll_compute_g200eh3,
|
|
.update = mgag200_pixpll_update_g200eh, // same as G200EH
|
|
};
|
|
|
|
/*
|
|
* G200ER
|
|
*/
|
|
|
|
static int mgag200_pixpll_compute_g200er(struct mgag200_pll *pixpll, long clock,
|
|
struct mgag200_pll_values *pixpllc)
|
|
{
|
|
static const unsigned int vcomax = 1488000;
|
|
static const unsigned int vcomin = 1056000;
|
|
static const unsigned int pllreffreq = 48000;
|
|
static const unsigned int m_div_val[] = { 1, 2, 4, 8 };
|
|
|
|
unsigned int delta, tmpdelta;
|
|
int testr, testn, testm, testo;
|
|
unsigned int p, m, n, s;
|
|
unsigned int computed, vco;
|
|
|
|
m = n = p = s = 0;
|
|
delta = 0xffffffff;
|
|
|
|
for (testr = 0; testr < 4; testr++) {
|
|
if (delta == 0)
|
|
break;
|
|
for (testn = 5; testn < 129; testn++) {
|
|
if (delta == 0)
|
|
break;
|
|
for (testm = 3; testm >= 0; testm--) {
|
|
if (delta == 0)
|
|
break;
|
|
for (testo = 5; testo < 33; testo++) {
|
|
vco = pllreffreq * (testn + 1) /
|
|
(testr + 1);
|
|
if (vco < vcomin)
|
|
continue;
|
|
if (vco > vcomax)
|
|
continue;
|
|
computed = vco / (m_div_val[testm] * (testo + 1));
|
|
if (computed > clock)
|
|
tmpdelta = computed - clock;
|
|
else
|
|
tmpdelta = clock - computed;
|
|
if (tmpdelta < delta) {
|
|
delta = tmpdelta;
|
|
m = (testm | (testo << 3)) + 1;
|
|
n = testn + 1;
|
|
p = testr + 1;
|
|
s = testr;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
pixpllc->m = m;
|
|
pixpllc->n = n;
|
|
pixpllc->p = p;
|
|
pixpllc->s = s;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
mgag200_pixpll_update_g200er(struct mgag200_pll *pixpll, const struct mgag200_pll_values *pixpllc)
|
|
{
|
|
unsigned int pixpllcm, pixpllcn, pixpllcp, pixpllcs;
|
|
u8 xpixpllcm, xpixpllcn, xpixpllcp, tmp;
|
|
struct mga_device *mdev = pixpll->mdev;
|
|
|
|
pixpllcm = pixpllc->m - 1;
|
|
pixpllcn = pixpllc->n - 1;
|
|
pixpllcp = pixpllc->p - 1;
|
|
pixpllcs = pixpllc->s;
|
|
|
|
xpixpllcm = pixpllcm;
|
|
xpixpllcn = pixpllcn;
|
|
xpixpllcp = (pixpllcs << 3) | pixpllcp;
|
|
|
|
WREG_MISC_MASKED(MGAREG_MISC_CLKSEL_MGA, MGAREG_MISC_CLKSEL_MASK);
|
|
|
|
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
|
tmp = RREG8(DAC_DATA);
|
|
tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
|
|
WREG8(DAC_DATA, tmp);
|
|
|
|
WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
|
|
tmp = RREG8(DAC_DATA);
|
|
tmp |= MGA1064_REMHEADCTL_CLKDIS;
|
|
WREG8(DAC_DATA, tmp);
|
|
|
|
tmp = RREG8(MGAREG_MEM_MISC_READ);
|
|
tmp |= (0x3<<2) | 0xc0;
|
|
WREG8(MGAREG_MEM_MISC_WRITE, tmp);
|
|
|
|
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
|
tmp = RREG8(DAC_DATA);
|
|
tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
|
|
tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
|
|
WREG8(DAC_DATA, tmp);
|
|
|
|
udelay(500);
|
|
|
|
WREG_DAC(MGA1064_ER_PIX_PLLC_N, xpixpllcn);
|
|
WREG_DAC(MGA1064_ER_PIX_PLLC_M, xpixpllcm);
|
|
WREG_DAC(MGA1064_ER_PIX_PLLC_P, xpixpllcp);
|
|
|
|
udelay(50);
|
|
}
|
|
|
|
static const struct mgag200_pll_funcs mgag200_pixpll_funcs_g200er = {
|
|
.compute = mgag200_pixpll_compute_g200er,
|
|
.update = mgag200_pixpll_update_g200er,
|
|
};
|
|
|
|
/*
|
|
* G200EW3
|
|
*/
|
|
|
|
static int mgag200_pixpll_compute_g200ew3(struct mgag200_pll *pixpll, long clock,
|
|
struct mgag200_pll_values *pixpllc)
|
|
{
|
|
static const unsigned int vcomax = 800000;
|
|
static const unsigned int vcomin = 400000;
|
|
static const unsigned int pllreffreq = 25000;
|
|
|
|
unsigned int delta, tmpdelta;
|
|
unsigned int testp, testm, testn, testp2;
|
|
unsigned int p, m, n, s;
|
|
unsigned int computed;
|
|
|
|
m = n = p = s = 0;
|
|
delta = 0xffffffff;
|
|
|
|
for (testp = 1; testp < 8; testp++) {
|
|
for (testp2 = 1; testp2 < 8; testp2++) {
|
|
if (testp < testp2)
|
|
continue;
|
|
if ((clock * testp * testp2) > vcomax)
|
|
continue;
|
|
if ((clock * testp * testp2) < vcomin)
|
|
continue;
|
|
for (testm = 1; testm < 26; testm++) {
|
|
for (testn = 32; testn < 2048 ; testn++) {
|
|
computed = (pllreffreq * testn) / (testm * testp * testp2);
|
|
if (computed > clock)
|
|
tmpdelta = computed - clock;
|
|
else
|
|
tmpdelta = clock - computed;
|
|
if (tmpdelta < delta) {
|
|
delta = tmpdelta;
|
|
m = testm + 1;
|
|
n = testn + 1;
|
|
p = testp + 1;
|
|
s = testp2;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
pixpllc->m = m;
|
|
pixpllc->n = n;
|
|
pixpllc->p = p;
|
|
pixpllc->s = s;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct mgag200_pll_funcs mgag200_pixpll_funcs_g200ew3 = {
|
|
.compute = mgag200_pixpll_compute_g200ew3,
|
|
.update = mgag200_pixpll_update_g200wb, // same as G200WB
|
|
};
|
|
|
|
/*
|
|
* PLL initialization
|
|
*/
|
|
|
|
int mgag200_pixpll_init(struct mgag200_pll *pixpll, struct mga_device *mdev)
|
|
{
|
|
struct drm_device *dev = &mdev->base;
|
|
|
|
pixpll->mdev = mdev;
|
|
|
|
switch (mdev->type) {
|
|
case G200_PCI:
|
|
case G200_AGP:
|
|
pixpll->funcs = &mgag200_pixpll_funcs_g200;
|
|
break;
|
|
case G200_SE_A:
|
|
case G200_SE_B:
|
|
if (mdev->model.g200se.unique_rev_id >= 0x04)
|
|
pixpll->funcs = &mgag200_pixpll_funcs_g200se_04;
|
|
else
|
|
pixpll->funcs = &mgag200_pixpll_funcs_g200se_00;
|
|
break;
|
|
case G200_WB:
|
|
pixpll->funcs = &mgag200_pixpll_funcs_g200wb;
|
|
break;
|
|
case G200_EV:
|
|
pixpll->funcs = &mgag200_pixpll_funcs_g200ev;
|
|
break;
|
|
case G200_EH:
|
|
pixpll->funcs = &mgag200_pixpll_funcs_g200eh;
|
|
break;
|
|
case G200_EH3:
|
|
pixpll->funcs = &mgag200_pixpll_funcs_g200eh3;
|
|
break;
|
|
case G200_ER:
|
|
pixpll->funcs = &mgag200_pixpll_funcs_g200er;
|
|
break;
|
|
case G200_EW3:
|
|
pixpll->funcs = &mgag200_pixpll_funcs_g200ew3;
|
|
break;
|
|
default:
|
|
drm_err(dev, "unknown device type %d\n", mdev->type);
|
|
return -ENODEV;
|
|
}
|
|
|
|
return 0;
|
|
}
|