132 lines
2.6 KiB
C
132 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0 OR MIT
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/* Copyright 2017-2019 Qiang Yu <yuq825@gmail.com> */
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#include <linux/iopoll.h>
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#include <linux/device.h>
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#include "lima_device.h"
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#include "lima_pmu.h"
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#include "lima_regs.h"
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#define pmu_write(reg, data) writel(data, ip->iomem + reg)
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#define pmu_read(reg) readl(ip->iomem + reg)
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static int lima_pmu_wait_cmd(struct lima_ip *ip)
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{
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struct lima_device *dev = ip->dev;
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int err;
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u32 v;
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err = readl_poll_timeout(ip->iomem + LIMA_PMU_INT_RAWSTAT,
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v, v & LIMA_PMU_INT_CMD_MASK,
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100, 100000);
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if (err) {
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dev_err(dev->dev, "timeout wait pmu cmd\n");
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return err;
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}
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pmu_write(LIMA_PMU_INT_CLEAR, LIMA_PMU_INT_CMD_MASK);
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return 0;
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}
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static u32 lima_pmu_get_ip_mask(struct lima_ip *ip)
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{
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struct lima_device *dev = ip->dev;
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u32 ret = 0;
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int i;
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ret |= LIMA_PMU_POWER_GP0_MASK;
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if (dev->id == lima_gpu_mali400) {
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ret |= LIMA_PMU_POWER_L2_MASK;
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for (i = 0; i < 4; i++) {
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if (dev->ip[lima_ip_pp0 + i].present)
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ret |= LIMA_PMU_POWER_PP_MASK(i);
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}
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} else {
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if (dev->ip[lima_ip_pp0].present)
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ret |= LIMA450_PMU_POWER_PP0_MASK;
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for (i = lima_ip_pp1; i <= lima_ip_pp3; i++) {
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if (dev->ip[i].present) {
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ret |= LIMA450_PMU_POWER_PP13_MASK;
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break;
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}
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}
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for (i = lima_ip_pp4; i <= lima_ip_pp7; i++) {
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if (dev->ip[i].present) {
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ret |= LIMA450_PMU_POWER_PP47_MASK;
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break;
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}
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}
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}
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return ret;
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}
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static int lima_pmu_hw_init(struct lima_ip *ip)
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{
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int err;
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u32 stat;
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pmu_write(LIMA_PMU_INT_MASK, 0);
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/* If this value is too low, when in high GPU clk freq,
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* GPU will be in unstable state.
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*/
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pmu_write(LIMA_PMU_SW_DELAY, 0xffff);
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/* status reg 1=off 0=on */
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stat = pmu_read(LIMA_PMU_STATUS);
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/* power up all ip */
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if (stat) {
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pmu_write(LIMA_PMU_POWER_UP, stat);
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err = lima_pmu_wait_cmd(ip);
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if (err)
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return err;
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}
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return 0;
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}
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static void lima_pmu_hw_fini(struct lima_ip *ip)
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{
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u32 stat;
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if (!ip->data.mask)
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ip->data.mask = lima_pmu_get_ip_mask(ip);
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stat = ~pmu_read(LIMA_PMU_STATUS) & ip->data.mask;
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if (stat) {
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pmu_write(LIMA_PMU_POWER_DOWN, stat);
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/* Don't wait for interrupt on Mali400 if all domains are
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* powered off because the HW won't generate an interrupt
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* in this case.
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*/
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if (ip->dev->id == lima_gpu_mali400)
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pmu_write(LIMA_PMU_INT_CLEAR, LIMA_PMU_INT_CMD_MASK);
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else
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lima_pmu_wait_cmd(ip);
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}
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}
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int lima_pmu_resume(struct lima_ip *ip)
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{
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return lima_pmu_hw_init(ip);
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}
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void lima_pmu_suspend(struct lima_ip *ip)
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{
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lima_pmu_hw_fini(ip);
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}
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int lima_pmu_init(struct lima_ip *ip)
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{
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return lima_pmu_hw_init(ip);
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}
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void lima_pmu_fini(struct lima_ip *ip)
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{
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lima_pmu_hw_fini(ip);
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}
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