425 lines
10 KiB
C
425 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2019 NXP.
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*/
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "dcss-dev.h"
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#define DCSS_CTXLD_CONTROL_STATUS 0x0
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#define CTXLD_ENABLE BIT(0)
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#define ARB_SEL BIT(1)
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#define RD_ERR_EN BIT(2)
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#define DB_COMP_EN BIT(3)
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#define SB_HP_COMP_EN BIT(4)
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#define SB_LP_COMP_EN BIT(5)
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#define DB_PEND_SB_REC_EN BIT(6)
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#define SB_PEND_DISP_ACTIVE_EN BIT(7)
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#define AHB_ERR_EN BIT(8)
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#define RD_ERR BIT(16)
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#define DB_COMP BIT(17)
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#define SB_HP_COMP BIT(18)
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#define SB_LP_COMP BIT(19)
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#define DB_PEND_SB_REC BIT(20)
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#define SB_PEND_DISP_ACTIVE BIT(21)
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#define AHB_ERR BIT(22)
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#define DCSS_CTXLD_DB_BASE_ADDR 0x10
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#define DCSS_CTXLD_DB_COUNT 0x14
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#define DCSS_CTXLD_SB_BASE_ADDR 0x18
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#define DCSS_CTXLD_SB_COUNT 0x1C
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#define SB_HP_COUNT_POS 0
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#define SB_HP_COUNT_MASK 0xffff
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#define SB_LP_COUNT_POS 16
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#define SB_LP_COUNT_MASK 0xffff0000
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#define DCSS_AHB_ERR_ADDR 0x20
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#define CTXLD_IRQ_COMPLETION (DB_COMP | SB_HP_COMP | SB_LP_COMP)
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#define CTXLD_IRQ_ERROR (RD_ERR | DB_PEND_SB_REC | AHB_ERR)
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/* The following sizes are in context loader entries, 8 bytes each. */
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#define CTXLD_DB_CTX_ENTRIES 1024 /* max 65536 */
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#define CTXLD_SB_LP_CTX_ENTRIES 10240 /* max 65536 */
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#define CTXLD_SB_HP_CTX_ENTRIES 20000 /* max 65536 */
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#define CTXLD_SB_CTX_ENTRIES (CTXLD_SB_LP_CTX_ENTRIES + \
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CTXLD_SB_HP_CTX_ENTRIES)
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/* Sizes, in entries, of the DB, SB_HP and SB_LP context regions. */
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static u16 dcss_ctxld_ctx_size[3] = {
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CTXLD_DB_CTX_ENTRIES,
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CTXLD_SB_HP_CTX_ENTRIES,
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CTXLD_SB_LP_CTX_ENTRIES
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};
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/* this represents an entry in the context loader map */
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struct dcss_ctxld_item {
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u32 val;
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u32 ofs;
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};
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#define CTX_ITEM_SIZE sizeof(struct dcss_ctxld_item)
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struct dcss_ctxld {
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struct device *dev;
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void __iomem *ctxld_reg;
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int irq;
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bool irq_en;
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struct dcss_ctxld_item *db[2];
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struct dcss_ctxld_item *sb_hp[2];
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struct dcss_ctxld_item *sb_lp[2];
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dma_addr_t db_paddr[2];
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dma_addr_t sb_paddr[2];
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u16 ctx_size[2][3]; /* holds the sizes of DB, SB_HP and SB_LP ctx */
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u8 current_ctx;
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bool in_use;
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bool armed;
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spinlock_t lock; /* protects concurent access to private data */
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};
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static irqreturn_t dcss_ctxld_irq_handler(int irq, void *data)
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{
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struct dcss_ctxld *ctxld = data;
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struct dcss_dev *dcss = dcss_drv_dev_to_dcss(ctxld->dev);
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u32 irq_status;
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irq_status = dcss_readl(ctxld->ctxld_reg + DCSS_CTXLD_CONTROL_STATUS);
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if (irq_status & CTXLD_IRQ_COMPLETION &&
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!(irq_status & CTXLD_ENABLE) && ctxld->in_use) {
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ctxld->in_use = false;
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if (dcss && dcss->disable_callback)
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dcss->disable_callback(dcss);
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} else if (irq_status & CTXLD_IRQ_ERROR) {
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/*
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* Except for throwing an error message and clearing the status
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* register, there's not much we can do here.
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*/
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dev_err(ctxld->dev, "ctxld: error encountered: %08x\n",
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irq_status);
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dev_err(ctxld->dev, "ctxld: db=%d, sb_hp=%d, sb_lp=%d\n",
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ctxld->ctx_size[ctxld->current_ctx ^ 1][CTX_DB],
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ctxld->ctx_size[ctxld->current_ctx ^ 1][CTX_SB_HP],
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ctxld->ctx_size[ctxld->current_ctx ^ 1][CTX_SB_LP]);
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}
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dcss_clr(irq_status & (CTXLD_IRQ_ERROR | CTXLD_IRQ_COMPLETION),
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ctxld->ctxld_reg + DCSS_CTXLD_CONTROL_STATUS);
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return IRQ_HANDLED;
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}
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static int dcss_ctxld_irq_config(struct dcss_ctxld *ctxld,
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struct platform_device *pdev)
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{
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int ret;
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ctxld->irq = platform_get_irq_byname(pdev, "ctxld");
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if (ctxld->irq < 0)
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return ctxld->irq;
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ret = request_irq(ctxld->irq, dcss_ctxld_irq_handler,
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0, "dcss_ctxld", ctxld);
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if (ret) {
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dev_err(ctxld->dev, "ctxld: irq request failed.\n");
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return ret;
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}
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ctxld->irq_en = true;
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return 0;
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}
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static void dcss_ctxld_hw_cfg(struct dcss_ctxld *ctxld)
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{
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dcss_writel(RD_ERR_EN | SB_HP_COMP_EN |
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DB_PEND_SB_REC_EN | AHB_ERR_EN | RD_ERR | AHB_ERR,
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ctxld->ctxld_reg + DCSS_CTXLD_CONTROL_STATUS);
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}
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static void dcss_ctxld_free_ctx(struct dcss_ctxld *ctxld)
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{
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struct dcss_ctxld_item *ctx;
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int i;
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for (i = 0; i < 2; i++) {
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if (ctxld->db[i]) {
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dma_free_coherent(ctxld->dev,
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CTXLD_DB_CTX_ENTRIES * sizeof(*ctx),
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ctxld->db[i], ctxld->db_paddr[i]);
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ctxld->db[i] = NULL;
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ctxld->db_paddr[i] = 0;
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}
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if (ctxld->sb_hp[i]) {
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dma_free_coherent(ctxld->dev,
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CTXLD_SB_CTX_ENTRIES * sizeof(*ctx),
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ctxld->sb_hp[i], ctxld->sb_paddr[i]);
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ctxld->sb_hp[i] = NULL;
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ctxld->sb_paddr[i] = 0;
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}
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}
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}
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static int dcss_ctxld_alloc_ctx(struct dcss_ctxld *ctxld)
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{
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struct dcss_ctxld_item *ctx;
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int i;
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for (i = 0; i < 2; i++) {
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ctx = dma_alloc_coherent(ctxld->dev,
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CTXLD_DB_CTX_ENTRIES * sizeof(*ctx),
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&ctxld->db_paddr[i], GFP_KERNEL);
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if (!ctx)
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return -ENOMEM;
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ctxld->db[i] = ctx;
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ctx = dma_alloc_coherent(ctxld->dev,
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CTXLD_SB_CTX_ENTRIES * sizeof(*ctx),
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&ctxld->sb_paddr[i], GFP_KERNEL);
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if (!ctx)
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return -ENOMEM;
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ctxld->sb_hp[i] = ctx;
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ctxld->sb_lp[i] = ctx + CTXLD_SB_HP_CTX_ENTRIES;
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}
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return 0;
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}
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int dcss_ctxld_init(struct dcss_dev *dcss, unsigned long ctxld_base)
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{
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struct dcss_ctxld *ctxld;
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int ret;
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ctxld = kzalloc(sizeof(*ctxld), GFP_KERNEL);
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if (!ctxld)
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return -ENOMEM;
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dcss->ctxld = ctxld;
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ctxld->dev = dcss->dev;
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spin_lock_init(&ctxld->lock);
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ret = dcss_ctxld_alloc_ctx(ctxld);
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if (ret) {
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dev_err(dcss->dev, "ctxld: cannot allocate context memory.\n");
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goto err;
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}
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ctxld->ctxld_reg = ioremap(ctxld_base, SZ_4K);
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if (!ctxld->ctxld_reg) {
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dev_err(dcss->dev, "ctxld: unable to remap ctxld base\n");
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ret = -ENOMEM;
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goto err;
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}
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ret = dcss_ctxld_irq_config(ctxld, to_platform_device(dcss->dev));
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if (ret)
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goto err_irq;
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dcss_ctxld_hw_cfg(ctxld);
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return 0;
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err_irq:
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iounmap(ctxld->ctxld_reg);
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err:
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dcss_ctxld_free_ctx(ctxld);
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kfree(ctxld);
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return ret;
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}
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void dcss_ctxld_exit(struct dcss_ctxld *ctxld)
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{
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free_irq(ctxld->irq, ctxld);
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if (ctxld->ctxld_reg)
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iounmap(ctxld->ctxld_reg);
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dcss_ctxld_free_ctx(ctxld);
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kfree(ctxld);
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}
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static int dcss_ctxld_enable_locked(struct dcss_ctxld *ctxld)
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{
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int curr_ctx = ctxld->current_ctx;
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u32 db_base, sb_base, sb_count;
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u32 sb_hp_cnt, sb_lp_cnt, db_cnt;
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struct dcss_dev *dcss = dcss_drv_dev_to_dcss(ctxld->dev);
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if (!dcss)
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return 0;
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dcss_dpr_write_sysctrl(dcss->dpr);
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dcss_scaler_write_sclctrl(dcss->scaler);
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sb_hp_cnt = ctxld->ctx_size[curr_ctx][CTX_SB_HP];
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sb_lp_cnt = ctxld->ctx_size[curr_ctx][CTX_SB_LP];
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db_cnt = ctxld->ctx_size[curr_ctx][CTX_DB];
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/* make sure SB_LP context area comes after SB_HP */
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if (sb_lp_cnt &&
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ctxld->sb_lp[curr_ctx] != ctxld->sb_hp[curr_ctx] + sb_hp_cnt) {
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struct dcss_ctxld_item *sb_lp_adjusted;
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sb_lp_adjusted = ctxld->sb_hp[curr_ctx] + sb_hp_cnt;
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memcpy(sb_lp_adjusted, ctxld->sb_lp[curr_ctx],
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sb_lp_cnt * CTX_ITEM_SIZE);
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}
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db_base = db_cnt ? ctxld->db_paddr[curr_ctx] : 0;
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dcss_writel(db_base, ctxld->ctxld_reg + DCSS_CTXLD_DB_BASE_ADDR);
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dcss_writel(db_cnt, ctxld->ctxld_reg + DCSS_CTXLD_DB_COUNT);
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if (sb_hp_cnt)
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sb_count = ((sb_hp_cnt << SB_HP_COUNT_POS) & SB_HP_COUNT_MASK) |
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((sb_lp_cnt << SB_LP_COUNT_POS) & SB_LP_COUNT_MASK);
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else
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sb_count = (sb_lp_cnt << SB_HP_COUNT_POS) & SB_HP_COUNT_MASK;
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sb_base = sb_count ? ctxld->sb_paddr[curr_ctx] : 0;
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dcss_writel(sb_base, ctxld->ctxld_reg + DCSS_CTXLD_SB_BASE_ADDR);
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dcss_writel(sb_count, ctxld->ctxld_reg + DCSS_CTXLD_SB_COUNT);
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/* enable the context loader */
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dcss_set(CTXLD_ENABLE, ctxld->ctxld_reg + DCSS_CTXLD_CONTROL_STATUS);
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ctxld->in_use = true;
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/*
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* Toggle the current context to the alternate one so that any updates
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* in the modules' settings take place there.
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*/
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ctxld->current_ctx ^= 1;
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ctxld->ctx_size[ctxld->current_ctx][CTX_DB] = 0;
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ctxld->ctx_size[ctxld->current_ctx][CTX_SB_HP] = 0;
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ctxld->ctx_size[ctxld->current_ctx][CTX_SB_LP] = 0;
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return 0;
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}
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int dcss_ctxld_enable(struct dcss_ctxld *ctxld)
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{
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spin_lock_irq(&ctxld->lock);
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ctxld->armed = true;
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spin_unlock_irq(&ctxld->lock);
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return 0;
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}
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void dcss_ctxld_kick(struct dcss_ctxld *ctxld)
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{
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unsigned long flags;
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spin_lock_irqsave(&ctxld->lock, flags);
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if (ctxld->armed && !ctxld->in_use) {
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ctxld->armed = false;
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dcss_ctxld_enable_locked(ctxld);
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}
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spin_unlock_irqrestore(&ctxld->lock, flags);
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}
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void dcss_ctxld_write_irqsafe(struct dcss_ctxld *ctxld, u32 ctx_id, u32 val,
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u32 reg_ofs)
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{
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int curr_ctx = ctxld->current_ctx;
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struct dcss_ctxld_item *ctx[] = {
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[CTX_DB] = ctxld->db[curr_ctx],
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[CTX_SB_HP] = ctxld->sb_hp[curr_ctx],
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[CTX_SB_LP] = ctxld->sb_lp[curr_ctx]
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};
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int item_idx = ctxld->ctx_size[curr_ctx][ctx_id];
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if (item_idx + 1 > dcss_ctxld_ctx_size[ctx_id]) {
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WARN_ON(1);
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return;
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}
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ctx[ctx_id][item_idx].val = val;
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ctx[ctx_id][item_idx].ofs = reg_ofs;
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ctxld->ctx_size[curr_ctx][ctx_id] += 1;
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}
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void dcss_ctxld_write(struct dcss_ctxld *ctxld, u32 ctx_id,
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u32 val, u32 reg_ofs)
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{
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spin_lock_irq(&ctxld->lock);
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dcss_ctxld_write_irqsafe(ctxld, ctx_id, val, reg_ofs);
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spin_unlock_irq(&ctxld->lock);
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}
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bool dcss_ctxld_is_flushed(struct dcss_ctxld *ctxld)
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{
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return ctxld->ctx_size[ctxld->current_ctx][CTX_DB] == 0 &&
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ctxld->ctx_size[ctxld->current_ctx][CTX_SB_HP] == 0 &&
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ctxld->ctx_size[ctxld->current_ctx][CTX_SB_LP] == 0;
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}
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int dcss_ctxld_resume(struct dcss_ctxld *ctxld)
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{
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dcss_ctxld_hw_cfg(ctxld);
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if (!ctxld->irq_en) {
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enable_irq(ctxld->irq);
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ctxld->irq_en = true;
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}
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return 0;
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}
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int dcss_ctxld_suspend(struct dcss_ctxld *ctxld)
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{
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int ret = 0;
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unsigned long timeout = jiffies + msecs_to_jiffies(500);
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if (!dcss_ctxld_is_flushed(ctxld)) {
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dcss_ctxld_kick(ctxld);
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while (!time_after(jiffies, timeout) && ctxld->in_use)
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msleep(20);
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if (time_after(jiffies, timeout))
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return -ETIMEDOUT;
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}
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spin_lock_irq(&ctxld->lock);
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if (ctxld->irq_en) {
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disable_irq_nosync(ctxld->irq);
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ctxld->irq_en = false;
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}
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/* reset context region and sizes */
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ctxld->current_ctx = 0;
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ctxld->ctx_size[0][CTX_DB] = 0;
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ctxld->ctx_size[0][CTX_SB_HP] = 0;
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ctxld->ctx_size[0][CTX_SB_LP] = 0;
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spin_unlock_irq(&ctxld->lock);
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return ret;
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}
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void dcss_ctxld_assert_locked(struct dcss_ctxld *ctxld)
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{
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lockdep_assert_held(&ctxld->lock);
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}
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