155 lines
4.1 KiB
C
155 lines
4.1 KiB
C
/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu_reset.h"
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#include "aldebaran.h"
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int amdgpu_reset_add_handler(struct amdgpu_reset_control *reset_ctl,
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struct amdgpu_reset_handler *handler)
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{
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/* TODO: Check if handler exists? */
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list_add_tail(&handler->handler_list, &reset_ctl->reset_handlers);
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return 0;
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}
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int amdgpu_reset_init(struct amdgpu_device *adev)
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{
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int ret = 0;
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switch (adev->ip_versions[MP1_HWIP][0]) {
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case IP_VERSION(13, 0, 2):
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ret = aldebaran_reset_init(adev);
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break;
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default:
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break;
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}
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return ret;
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}
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int amdgpu_reset_fini(struct amdgpu_device *adev)
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{
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int ret = 0;
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switch (adev->ip_versions[MP1_HWIP][0]) {
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case IP_VERSION(13, 0, 2):
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ret = aldebaran_reset_fini(adev);
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break;
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default:
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break;
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}
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return ret;
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}
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int amdgpu_reset_prepare_hwcontext(struct amdgpu_device *adev,
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struct amdgpu_reset_context *reset_context)
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{
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struct amdgpu_reset_handler *reset_handler = NULL;
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if (adev->reset_cntl && adev->reset_cntl->get_reset_handler)
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reset_handler = adev->reset_cntl->get_reset_handler(
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adev->reset_cntl, reset_context);
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if (!reset_handler)
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return -ENOSYS;
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return reset_handler->prepare_hwcontext(adev->reset_cntl,
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reset_context);
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}
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int amdgpu_reset_perform_reset(struct amdgpu_device *adev,
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struct amdgpu_reset_context *reset_context)
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{
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int ret;
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struct amdgpu_reset_handler *reset_handler = NULL;
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if (adev->reset_cntl)
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reset_handler = adev->reset_cntl->get_reset_handler(
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adev->reset_cntl, reset_context);
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if (!reset_handler)
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return -ENOSYS;
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ret = reset_handler->perform_reset(adev->reset_cntl, reset_context);
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if (ret)
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return ret;
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return reset_handler->restore_hwcontext(adev->reset_cntl,
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reset_context);
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}
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void amdgpu_reset_destroy_reset_domain(struct kref *ref)
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{
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struct amdgpu_reset_domain *reset_domain = container_of(ref,
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struct amdgpu_reset_domain,
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refcount);
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if (reset_domain->wq)
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destroy_workqueue(reset_domain->wq);
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kvfree(reset_domain);
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}
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struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_domain_type type,
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char *wq_name)
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{
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struct amdgpu_reset_domain *reset_domain;
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reset_domain = kvzalloc(sizeof(struct amdgpu_reset_domain), GFP_KERNEL);
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if (!reset_domain) {
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DRM_ERROR("Failed to allocate amdgpu_reset_domain!");
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return NULL;
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}
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reset_domain->type = type;
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kref_init(&reset_domain->refcount);
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reset_domain->wq = create_singlethread_workqueue(wq_name);
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if (!reset_domain->wq) {
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DRM_ERROR("Failed to allocate wq for amdgpu_reset_domain!");
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amdgpu_reset_put_reset_domain(reset_domain);
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return NULL;
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}
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atomic_set(&reset_domain->in_gpu_reset, 0);
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init_rwsem(&reset_domain->sem);
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return reset_domain;
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}
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void amdgpu_device_lock_reset_domain(struct amdgpu_reset_domain *reset_domain)
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{
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atomic_set(&reset_domain->in_gpu_reset, 1);
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down_write(&reset_domain->sem);
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}
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void amdgpu_device_unlock_reset_domain(struct amdgpu_reset_domain *reset_domain)
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{
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atomic_set(&reset_domain->in_gpu_reset, 0);
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up_write(&reset_domain->sem);
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}
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