324 lines
8.9 KiB
C
324 lines
8.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* FPGA Manager Driver for FPGA Management Engine (FME)
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*
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* Copyright (C) 2017-2018 Intel Corporation, Inc.
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*
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* Authors:
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* Kang Luwei <luwei.kang@intel.com>
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* Xiao Guangrong <guangrong.xiao@linux.intel.com>
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* Wu Hao <hao.wu@intel.com>
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* Joseph Grecco <joe.grecco@intel.com>
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* Enno Luebbers <enno.luebbers@intel.com>
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* Tim Whisonant <tim.whisonant@intel.com>
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* Ananda Ravuri <ananda.ravuri@intel.com>
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* Christopher Rauer <christopher.rauer@intel.com>
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* Henry Mitchel <henry.mitchel@intel.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/module.h>
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#include <linux/iopoll.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/fpga/fpga-mgr.h>
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#include "dfl-fme-pr.h"
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/* FME Partial Reconfiguration Sub Feature Register Set */
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#define FME_PR_DFH 0x0
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#define FME_PR_CTRL 0x8
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#define FME_PR_STS 0x10
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#define FME_PR_DATA 0x18
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#define FME_PR_ERR 0x20
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#define FME_PR_INTFC_ID_L 0xA8
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#define FME_PR_INTFC_ID_H 0xB0
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/* FME PR Control Register Bitfield */
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#define FME_PR_CTRL_PR_RST BIT_ULL(0) /* Reset PR engine */
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#define FME_PR_CTRL_PR_RSTACK BIT_ULL(4) /* Ack for PR engine reset */
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#define FME_PR_CTRL_PR_RGN_ID GENMASK_ULL(9, 7) /* PR Region ID */
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#define FME_PR_CTRL_PR_START BIT_ULL(12) /* Start to request PR service */
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#define FME_PR_CTRL_PR_COMPLETE BIT_ULL(13) /* PR data push completion */
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/* FME PR Status Register Bitfield */
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/* Number of available entries in HW queue inside the PR engine. */
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#define FME_PR_STS_PR_CREDIT GENMASK_ULL(8, 0)
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#define FME_PR_STS_PR_STS BIT_ULL(16) /* PR operation status */
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#define FME_PR_STS_PR_STS_IDLE 0
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#define FME_PR_STS_PR_CTRLR_STS GENMASK_ULL(22, 20) /* Controller status */
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#define FME_PR_STS_PR_HOST_STS GENMASK_ULL(27, 24) /* PR host status */
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/* FME PR Data Register Bitfield */
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/* PR data from the raw-binary file. */
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#define FME_PR_DATA_PR_DATA_RAW GENMASK_ULL(32, 0)
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/* FME PR Error Register */
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/* PR Operation errors detected. */
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#define FME_PR_ERR_OPERATION_ERR BIT_ULL(0)
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/* CRC error detected. */
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#define FME_PR_ERR_CRC_ERR BIT_ULL(1)
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/* Incompatible PR bitstream detected. */
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#define FME_PR_ERR_INCOMPATIBLE_BS BIT_ULL(2)
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/* PR data push protocol violated. */
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#define FME_PR_ERR_PROTOCOL_ERR BIT_ULL(3)
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/* PR data fifo overflow error detected */
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#define FME_PR_ERR_FIFO_OVERFLOW BIT_ULL(4)
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#define PR_WAIT_TIMEOUT 8000000
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#define PR_HOST_STATUS_IDLE 0
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struct fme_mgr_priv {
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void __iomem *ioaddr;
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u64 pr_error;
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};
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static u64 pr_error_to_mgr_status(u64 err)
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{
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u64 status = 0;
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if (err & FME_PR_ERR_OPERATION_ERR)
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status |= FPGA_MGR_STATUS_OPERATION_ERR;
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if (err & FME_PR_ERR_CRC_ERR)
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status |= FPGA_MGR_STATUS_CRC_ERR;
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if (err & FME_PR_ERR_INCOMPATIBLE_BS)
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status |= FPGA_MGR_STATUS_INCOMPATIBLE_IMAGE_ERR;
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if (err & FME_PR_ERR_PROTOCOL_ERR)
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status |= FPGA_MGR_STATUS_IP_PROTOCOL_ERR;
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if (err & FME_PR_ERR_FIFO_OVERFLOW)
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status |= FPGA_MGR_STATUS_FIFO_OVERFLOW_ERR;
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return status;
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}
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static u64 fme_mgr_pr_error_handle(void __iomem *fme_pr)
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{
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u64 pr_status, pr_error;
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pr_status = readq(fme_pr + FME_PR_STS);
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if (!(pr_status & FME_PR_STS_PR_STS))
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return 0;
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pr_error = readq(fme_pr + FME_PR_ERR);
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writeq(pr_error, fme_pr + FME_PR_ERR);
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return pr_error;
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}
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static int fme_mgr_write_init(struct fpga_manager *mgr,
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struct fpga_image_info *info,
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const char *buf, size_t count)
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{
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struct device *dev = &mgr->dev;
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struct fme_mgr_priv *priv = mgr->priv;
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void __iomem *fme_pr = priv->ioaddr;
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u64 pr_ctrl, pr_status;
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if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
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dev_err(dev, "only supports partial reconfiguration.\n");
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return -EINVAL;
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}
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dev_dbg(dev, "resetting PR before initiated PR\n");
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pr_ctrl = readq(fme_pr + FME_PR_CTRL);
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pr_ctrl |= FME_PR_CTRL_PR_RST;
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writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
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if (readq_poll_timeout(fme_pr + FME_PR_CTRL, pr_ctrl,
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pr_ctrl & FME_PR_CTRL_PR_RSTACK, 1,
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PR_WAIT_TIMEOUT)) {
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dev_err(dev, "PR Reset ACK timeout\n");
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return -ETIMEDOUT;
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}
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pr_ctrl = readq(fme_pr + FME_PR_CTRL);
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pr_ctrl &= ~FME_PR_CTRL_PR_RST;
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writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
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dev_dbg(dev,
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"waiting for PR resource in HW to be initialized and ready\n");
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if (readq_poll_timeout(fme_pr + FME_PR_STS, pr_status,
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(pr_status & FME_PR_STS_PR_STS) ==
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FME_PR_STS_PR_STS_IDLE, 1, PR_WAIT_TIMEOUT)) {
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dev_err(dev, "PR Status timeout\n");
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priv->pr_error = fme_mgr_pr_error_handle(fme_pr);
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return -ETIMEDOUT;
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}
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dev_dbg(dev, "check and clear previous PR error\n");
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priv->pr_error = fme_mgr_pr_error_handle(fme_pr);
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if (priv->pr_error)
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dev_dbg(dev, "previous PR error detected %llx\n",
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(unsigned long long)priv->pr_error);
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dev_dbg(dev, "set PR port ID\n");
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pr_ctrl = readq(fme_pr + FME_PR_CTRL);
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pr_ctrl &= ~FME_PR_CTRL_PR_RGN_ID;
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pr_ctrl |= FIELD_PREP(FME_PR_CTRL_PR_RGN_ID, info->region_id);
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writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
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return 0;
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}
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static int fme_mgr_write(struct fpga_manager *mgr,
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const char *buf, size_t count)
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{
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struct device *dev = &mgr->dev;
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struct fme_mgr_priv *priv = mgr->priv;
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void __iomem *fme_pr = priv->ioaddr;
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u64 pr_ctrl, pr_status, pr_data;
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int delay = 0, pr_credit, i = 0;
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dev_dbg(dev, "start request\n");
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pr_ctrl = readq(fme_pr + FME_PR_CTRL);
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pr_ctrl |= FME_PR_CTRL_PR_START;
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writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
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dev_dbg(dev, "pushing data from bitstream to HW\n");
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/*
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* driver can push data to PR hardware using PR_DATA register once HW
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* has enough pr_credit (> 1), pr_credit reduces one for every 32bit
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* pr data write to PR_DATA register. If pr_credit <= 1, driver needs
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* to wait for enough pr_credit from hardware by polling.
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*/
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pr_status = readq(fme_pr + FME_PR_STS);
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pr_credit = FIELD_GET(FME_PR_STS_PR_CREDIT, pr_status);
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while (count > 0) {
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while (pr_credit <= 1) {
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if (delay++ > PR_WAIT_TIMEOUT) {
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dev_err(dev, "PR_CREDIT timeout\n");
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return -ETIMEDOUT;
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}
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udelay(1);
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pr_status = readq(fme_pr + FME_PR_STS);
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pr_credit = FIELD_GET(FME_PR_STS_PR_CREDIT, pr_status);
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}
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if (count < 4) {
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dev_err(dev, "Invalid PR bitstream size\n");
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return -EINVAL;
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}
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pr_data = 0;
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pr_data |= FIELD_PREP(FME_PR_DATA_PR_DATA_RAW,
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*(((u32 *)buf) + i));
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writeq(pr_data, fme_pr + FME_PR_DATA);
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count -= 4;
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pr_credit--;
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i++;
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}
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return 0;
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}
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static int fme_mgr_write_complete(struct fpga_manager *mgr,
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struct fpga_image_info *info)
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{
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struct device *dev = &mgr->dev;
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struct fme_mgr_priv *priv = mgr->priv;
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void __iomem *fme_pr = priv->ioaddr;
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u64 pr_ctrl;
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pr_ctrl = readq(fme_pr + FME_PR_CTRL);
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pr_ctrl |= FME_PR_CTRL_PR_COMPLETE;
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writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
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dev_dbg(dev, "green bitstream push complete\n");
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dev_dbg(dev, "waiting for HW to release PR resource\n");
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if (readq_poll_timeout(fme_pr + FME_PR_CTRL, pr_ctrl,
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!(pr_ctrl & FME_PR_CTRL_PR_START), 1,
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PR_WAIT_TIMEOUT)) {
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dev_err(dev, "PR Completion ACK timeout.\n");
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return -ETIMEDOUT;
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}
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dev_dbg(dev, "PR operation complete, checking status\n");
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priv->pr_error = fme_mgr_pr_error_handle(fme_pr);
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if (priv->pr_error) {
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dev_dbg(dev, "PR error detected %llx\n",
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(unsigned long long)priv->pr_error);
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return -EIO;
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}
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dev_dbg(dev, "PR done successfully\n");
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return 0;
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}
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static u64 fme_mgr_status(struct fpga_manager *mgr)
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{
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struct fme_mgr_priv *priv = mgr->priv;
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return pr_error_to_mgr_status(priv->pr_error);
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}
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static const struct fpga_manager_ops fme_mgr_ops = {
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.write_init = fme_mgr_write_init,
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.write = fme_mgr_write,
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.write_complete = fme_mgr_write_complete,
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.status = fme_mgr_status,
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};
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static void fme_mgr_get_compat_id(void __iomem *fme_pr,
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struct fpga_compat_id *id)
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{
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id->id_l = readq(fme_pr + FME_PR_INTFC_ID_L);
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id->id_h = readq(fme_pr + FME_PR_INTFC_ID_H);
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}
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static int fme_mgr_probe(struct platform_device *pdev)
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{
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struct dfl_fme_mgr_pdata *pdata = dev_get_platdata(&pdev->dev);
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struct fpga_manager_info info = { 0 };
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struct device *dev = &pdev->dev;
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struct fme_mgr_priv *priv;
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struct fpga_manager *mgr;
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struct resource *res;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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if (pdata->ioaddr)
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priv->ioaddr = pdata->ioaddr;
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if (!priv->ioaddr) {
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->ioaddr = devm_ioremap_resource(dev, res);
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if (IS_ERR(priv->ioaddr))
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return PTR_ERR(priv->ioaddr);
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}
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info.name = "DFL FME FPGA Manager";
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info.mops = &fme_mgr_ops;
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info.priv = priv;
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info.compat_id = devm_kzalloc(dev, sizeof(*info.compat_id), GFP_KERNEL);
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if (!info.compat_id)
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return -ENOMEM;
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fme_mgr_get_compat_id(priv->ioaddr, info.compat_id);
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mgr = devm_fpga_mgr_register_full(dev, &info);
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return PTR_ERR_OR_ZERO(mgr);
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}
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static struct platform_driver fme_mgr_driver = {
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.driver = {
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.name = DFL_FPGA_FME_MGR,
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},
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.probe = fme_mgr_probe,
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};
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module_platform_driver(fme_mgr_driver);
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MODULE_DESCRIPTION("FPGA Manager for DFL FPGA Management Engine");
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MODULE_AUTHOR("Intel Corporation");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:dfl-fme-mgr");
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