598 lines
16 KiB
C
598 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* amd8111_edac.c, AMD8111 Hyper Transport chip EDAC kernel module
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*
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* Copyright (c) 2008 Wind River Systems, Inc.
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*
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* Authors: Cao Qingtao <qingtao.cao@windriver.com>
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* Benjamin Walsh <benjamin.walsh@windriver.com>
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* Hu Yongqi <yongqi.hu@windriver.com>
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/bitops.h>
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#include <linux/edac.h>
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#include <linux/pci_ids.h>
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#include <asm/io.h>
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#include "edac_module.h"
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#include "amd8111_edac.h"
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#define AMD8111_EDAC_REVISION " Ver: 1.0.0"
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#define AMD8111_EDAC_MOD_STR "amd8111_edac"
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#define PCI_DEVICE_ID_AMD_8111_PCI 0x7460
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enum amd8111_edac_devs {
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LPC_BRIDGE = 0,
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};
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enum amd8111_edac_pcis {
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PCI_BRIDGE = 0,
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};
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/* Wrapper functions for accessing PCI configuration space */
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static int edac_pci_read_dword(struct pci_dev *dev, int reg, u32 *val32)
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{
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int ret;
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ret = pci_read_config_dword(dev, reg, val32);
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if (ret != 0)
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printk(KERN_ERR AMD8111_EDAC_MOD_STR
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" PCI Access Read Error at 0x%x\n", reg);
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return ret;
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}
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static void edac_pci_read_byte(struct pci_dev *dev, int reg, u8 *val8)
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{
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int ret;
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ret = pci_read_config_byte(dev, reg, val8);
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if (ret != 0)
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printk(KERN_ERR AMD8111_EDAC_MOD_STR
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" PCI Access Read Error at 0x%x\n", reg);
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}
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static void edac_pci_write_dword(struct pci_dev *dev, int reg, u32 val32)
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{
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int ret;
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ret = pci_write_config_dword(dev, reg, val32);
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if (ret != 0)
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printk(KERN_ERR AMD8111_EDAC_MOD_STR
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" PCI Access Write Error at 0x%x\n", reg);
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}
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static void edac_pci_write_byte(struct pci_dev *dev, int reg, u8 val8)
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{
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int ret;
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ret = pci_write_config_byte(dev, reg, val8);
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if (ret != 0)
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printk(KERN_ERR AMD8111_EDAC_MOD_STR
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" PCI Access Write Error at 0x%x\n", reg);
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}
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/*
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* device-specific methods for amd8111 PCI Bridge Controller
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*
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* Error Reporting and Handling for amd8111 chipset could be found
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* in its datasheet 3.1.2 section, P37
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*/
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static void amd8111_pci_bridge_init(struct amd8111_pci_info *pci_info)
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{
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u32 val32;
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struct pci_dev *dev = pci_info->dev;
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/* First clear error detection flags on the host interface */
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/* Clear SSE/SMA/STA flags in the global status register*/
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edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32);
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if (val32 & PCI_STSCMD_CLEAR_MASK)
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edac_pci_write_dword(dev, REG_PCI_STSCMD, val32);
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/* Clear CRC and Link Fail flags in HT Link Control reg */
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edac_pci_read_dword(dev, REG_HT_LINK, &val32);
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if (val32 & HT_LINK_CLEAR_MASK)
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edac_pci_write_dword(dev, REG_HT_LINK, val32);
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/* Second clear all fault on the secondary interface */
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/* Clear error flags in the memory-base limit reg. */
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edac_pci_read_dword(dev, REG_MEM_LIM, &val32);
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if (val32 & MEM_LIMIT_CLEAR_MASK)
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edac_pci_write_dword(dev, REG_MEM_LIM, val32);
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/* Clear Discard Timer Expired flag in Interrupt/Bridge Control reg */
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edac_pci_read_dword(dev, REG_PCI_INTBRG_CTRL, &val32);
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if (val32 & PCI_INTBRG_CTRL_CLEAR_MASK)
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edac_pci_write_dword(dev, REG_PCI_INTBRG_CTRL, val32);
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/* Last enable error detections */
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if (edac_op_state == EDAC_OPSTATE_POLL) {
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/* Enable System Error reporting in global status register */
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edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32);
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val32 |= PCI_STSCMD_SERREN;
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edac_pci_write_dword(dev, REG_PCI_STSCMD, val32);
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/* Enable CRC Sync flood packets to HyperTransport Link */
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edac_pci_read_dword(dev, REG_HT_LINK, &val32);
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val32 |= HT_LINK_CRCFEN;
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edac_pci_write_dword(dev, REG_HT_LINK, val32);
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/* Enable SSE reporting etc in Interrupt control reg */
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edac_pci_read_dword(dev, REG_PCI_INTBRG_CTRL, &val32);
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val32 |= PCI_INTBRG_CTRL_POLL_MASK;
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edac_pci_write_dword(dev, REG_PCI_INTBRG_CTRL, val32);
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}
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}
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static void amd8111_pci_bridge_exit(struct amd8111_pci_info *pci_info)
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{
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u32 val32;
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struct pci_dev *dev = pci_info->dev;
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if (edac_op_state == EDAC_OPSTATE_POLL) {
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/* Disable System Error reporting */
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edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32);
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val32 &= ~PCI_STSCMD_SERREN;
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edac_pci_write_dword(dev, REG_PCI_STSCMD, val32);
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/* Disable CRC flood packets */
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edac_pci_read_dword(dev, REG_HT_LINK, &val32);
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val32 &= ~HT_LINK_CRCFEN;
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edac_pci_write_dword(dev, REG_HT_LINK, val32);
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/* Disable DTSERREN/MARSP/SERREN in Interrupt Control reg */
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edac_pci_read_dword(dev, REG_PCI_INTBRG_CTRL, &val32);
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val32 &= ~PCI_INTBRG_CTRL_POLL_MASK;
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edac_pci_write_dword(dev, REG_PCI_INTBRG_CTRL, val32);
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}
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}
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static void amd8111_pci_bridge_check(struct edac_pci_ctl_info *edac_dev)
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{
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struct amd8111_pci_info *pci_info = edac_dev->pvt_info;
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struct pci_dev *dev = pci_info->dev;
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u32 val32;
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/* Check out PCI Bridge Status and Command Register */
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edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32);
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if (val32 & PCI_STSCMD_CLEAR_MASK) {
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printk(KERN_INFO "Error(s) in PCI bridge status and command"
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"register on device %s\n", pci_info->ctl_name);
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printk(KERN_INFO "SSE: %d, RMA: %d, RTA: %d\n",
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(val32 & PCI_STSCMD_SSE) != 0,
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(val32 & PCI_STSCMD_RMA) != 0,
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(val32 & PCI_STSCMD_RTA) != 0);
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val32 |= PCI_STSCMD_CLEAR_MASK;
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edac_pci_write_dword(dev, REG_PCI_STSCMD, val32);
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edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
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}
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/* Check out HyperTransport Link Control Register */
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edac_pci_read_dword(dev, REG_HT_LINK, &val32);
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if (val32 & HT_LINK_LKFAIL) {
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printk(KERN_INFO "Error(s) in hypertransport link control"
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"register on device %s\n", pci_info->ctl_name);
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printk(KERN_INFO "LKFAIL: %d\n",
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(val32 & HT_LINK_LKFAIL) != 0);
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val32 |= HT_LINK_LKFAIL;
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edac_pci_write_dword(dev, REG_HT_LINK, val32);
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edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
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}
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/* Check out PCI Interrupt and Bridge Control Register */
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edac_pci_read_dword(dev, REG_PCI_INTBRG_CTRL, &val32);
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if (val32 & PCI_INTBRG_CTRL_DTSTAT) {
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printk(KERN_INFO "Error(s) in PCI interrupt and bridge control"
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"register on device %s\n", pci_info->ctl_name);
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printk(KERN_INFO "DTSTAT: %d\n",
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(val32 & PCI_INTBRG_CTRL_DTSTAT) != 0);
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val32 |= PCI_INTBRG_CTRL_DTSTAT;
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edac_pci_write_dword(dev, REG_PCI_INTBRG_CTRL, val32);
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edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
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}
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/* Check out PCI Bridge Memory Base-Limit Register */
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edac_pci_read_dword(dev, REG_MEM_LIM, &val32);
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if (val32 & MEM_LIMIT_CLEAR_MASK) {
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printk(KERN_INFO
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"Error(s) in mem limit register on %s device\n",
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pci_info->ctl_name);
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printk(KERN_INFO "DPE: %d, RSE: %d, RMA: %d\n"
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"RTA: %d, STA: %d, MDPE: %d\n",
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(val32 & MEM_LIMIT_DPE) != 0,
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(val32 & MEM_LIMIT_RSE) != 0,
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(val32 & MEM_LIMIT_RMA) != 0,
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(val32 & MEM_LIMIT_RTA) != 0,
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(val32 & MEM_LIMIT_STA) != 0,
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(val32 & MEM_LIMIT_MDPE) != 0);
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val32 |= MEM_LIMIT_CLEAR_MASK;
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edac_pci_write_dword(dev, REG_MEM_LIM, val32);
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edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
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}
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}
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static struct resource *legacy_io_res;
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static int at_compat_reg_broken;
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#define LEGACY_NR_PORTS 1
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/* device-specific methods for amd8111 LPC Bridge device */
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static void amd8111_lpc_bridge_init(struct amd8111_dev_info *dev_info)
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{
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u8 val8;
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struct pci_dev *dev = dev_info->dev;
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/* First clear REG_AT_COMPAT[SERR, IOCHK] if necessary */
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legacy_io_res = request_region(REG_AT_COMPAT, LEGACY_NR_PORTS,
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AMD8111_EDAC_MOD_STR);
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if (!legacy_io_res)
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printk(KERN_INFO "%s: failed to request legacy I/O region "
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"start %d, len %d\n", __func__,
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REG_AT_COMPAT, LEGACY_NR_PORTS);
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else {
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val8 = __do_inb(REG_AT_COMPAT);
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if (val8 == 0xff) { /* buggy port */
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printk(KERN_INFO "%s: port %d is buggy, not supported"
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" by hardware?\n", __func__, REG_AT_COMPAT);
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at_compat_reg_broken = 1;
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release_region(REG_AT_COMPAT, LEGACY_NR_PORTS);
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legacy_io_res = NULL;
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} else {
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u8 out8 = 0;
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if (val8 & AT_COMPAT_SERR)
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out8 = AT_COMPAT_CLRSERR;
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if (val8 & AT_COMPAT_IOCHK)
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out8 |= AT_COMPAT_CLRIOCHK;
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if (out8 > 0)
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__do_outb(out8, REG_AT_COMPAT);
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}
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}
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/* Second clear error flags on LPC bridge */
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edac_pci_read_byte(dev, REG_IO_CTRL_1, &val8);
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if (val8 & IO_CTRL_1_CLEAR_MASK)
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edac_pci_write_byte(dev, REG_IO_CTRL_1, val8);
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}
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static void amd8111_lpc_bridge_exit(struct amd8111_dev_info *dev_info)
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{
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if (legacy_io_res)
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release_region(REG_AT_COMPAT, LEGACY_NR_PORTS);
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}
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static void amd8111_lpc_bridge_check(struct edac_device_ctl_info *edac_dev)
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{
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struct amd8111_dev_info *dev_info = edac_dev->pvt_info;
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struct pci_dev *dev = dev_info->dev;
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u8 val8;
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edac_pci_read_byte(dev, REG_IO_CTRL_1, &val8);
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if (val8 & IO_CTRL_1_CLEAR_MASK) {
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printk(KERN_INFO
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"Error(s) in IO control register on %s device\n",
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dev_info->ctl_name);
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printk(KERN_INFO "LPC ERR: %d, PW2LPC: %d\n",
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(val8 & IO_CTRL_1_LPC_ERR) != 0,
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(val8 & IO_CTRL_1_PW2LPC) != 0);
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val8 |= IO_CTRL_1_CLEAR_MASK;
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edac_pci_write_byte(dev, REG_IO_CTRL_1, val8);
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edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
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}
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if (at_compat_reg_broken == 0) {
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u8 out8 = 0;
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val8 = __do_inb(REG_AT_COMPAT);
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if (val8 & AT_COMPAT_SERR)
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out8 = AT_COMPAT_CLRSERR;
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if (val8 & AT_COMPAT_IOCHK)
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out8 |= AT_COMPAT_CLRIOCHK;
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if (out8 > 0) {
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__do_outb(out8, REG_AT_COMPAT);
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edac_device_handle_ue(edac_dev, 0, 0,
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edac_dev->ctl_name);
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}
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}
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}
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/* General devices represented by edac_device_ctl_info */
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static struct amd8111_dev_info amd8111_devices[] = {
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[LPC_BRIDGE] = {
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.err_dev = PCI_DEVICE_ID_AMD_8111_LPC,
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.ctl_name = "lpc",
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.init = amd8111_lpc_bridge_init,
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.exit = amd8111_lpc_bridge_exit,
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.check = amd8111_lpc_bridge_check,
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},
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{0},
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};
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/* PCI controllers represented by edac_pci_ctl_info */
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static struct amd8111_pci_info amd8111_pcis[] = {
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[PCI_BRIDGE] = {
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.err_dev = PCI_DEVICE_ID_AMD_8111_PCI,
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.ctl_name = "AMD8111_PCI_Controller",
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.init = amd8111_pci_bridge_init,
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.exit = amd8111_pci_bridge_exit,
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.check = amd8111_pci_bridge_check,
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},
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{0},
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};
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static int amd8111_dev_probe(struct pci_dev *dev,
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const struct pci_device_id *id)
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{
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struct amd8111_dev_info *dev_info = &amd8111_devices[id->driver_data];
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int ret = -ENODEV;
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dev_info->dev = pci_get_device(PCI_VENDOR_ID_AMD,
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dev_info->err_dev, NULL);
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if (!dev_info->dev) {
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printk(KERN_ERR "EDAC device not found:"
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"vendor %x, device %x, name %s\n",
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PCI_VENDOR_ID_AMD, dev_info->err_dev,
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dev_info->ctl_name);
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goto err;
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}
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if (pci_enable_device(dev_info->dev)) {
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printk(KERN_ERR "failed to enable:"
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"vendor %x, device %x, name %s\n",
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PCI_VENDOR_ID_AMD, dev_info->err_dev,
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dev_info->ctl_name);
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goto err_dev_put;
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}
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/*
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* we do not allocate extra private structure for
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* edac_device_ctl_info, but make use of existing
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* one instead.
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*/
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dev_info->edac_idx = edac_device_alloc_index();
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dev_info->edac_dev =
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edac_device_alloc_ctl_info(0, dev_info->ctl_name, 1,
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NULL, 0, 0,
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NULL, 0, dev_info->edac_idx);
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if (!dev_info->edac_dev) {
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ret = -ENOMEM;
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goto err_dev_put;
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}
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dev_info->edac_dev->pvt_info = dev_info;
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dev_info->edac_dev->dev = &dev_info->dev->dev;
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dev_info->edac_dev->mod_name = AMD8111_EDAC_MOD_STR;
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dev_info->edac_dev->ctl_name = dev_info->ctl_name;
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dev_info->edac_dev->dev_name = dev_name(&dev_info->dev->dev);
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if (edac_op_state == EDAC_OPSTATE_POLL)
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dev_info->edac_dev->edac_check = dev_info->check;
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if (dev_info->init)
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dev_info->init(dev_info);
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if (edac_device_add_device(dev_info->edac_dev) > 0) {
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printk(KERN_ERR "failed to add edac_dev for %s\n",
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dev_info->ctl_name);
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goto err_edac_free_ctl;
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}
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printk(KERN_INFO "added one edac_dev on AMD8111 "
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"vendor %x, device %x, name %s\n",
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PCI_VENDOR_ID_AMD, dev_info->err_dev,
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dev_info->ctl_name);
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return 0;
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err_edac_free_ctl:
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edac_device_free_ctl_info(dev_info->edac_dev);
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err_dev_put:
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pci_dev_put(dev_info->dev);
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err:
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return ret;
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}
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static void amd8111_dev_remove(struct pci_dev *dev)
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{
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struct amd8111_dev_info *dev_info;
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for (dev_info = amd8111_devices; dev_info->err_dev; dev_info++)
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if (dev_info->dev->device == dev->device)
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break;
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if (!dev_info->err_dev) /* should never happen */
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return;
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if (dev_info->edac_dev) {
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edac_device_del_device(dev_info->edac_dev->dev);
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edac_device_free_ctl_info(dev_info->edac_dev);
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}
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if (dev_info->exit)
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dev_info->exit(dev_info);
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pci_dev_put(dev_info->dev);
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}
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static int amd8111_pci_probe(struct pci_dev *dev,
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const struct pci_device_id *id)
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{
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struct amd8111_pci_info *pci_info = &amd8111_pcis[id->driver_data];
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int ret = -ENODEV;
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pci_info->dev = pci_get_device(PCI_VENDOR_ID_AMD,
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pci_info->err_dev, NULL);
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if (!pci_info->dev) {
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printk(KERN_ERR "EDAC device not found:"
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"vendor %x, device %x, name %s\n",
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PCI_VENDOR_ID_AMD, pci_info->err_dev,
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pci_info->ctl_name);
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goto err;
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|
}
|
|
|
|
if (pci_enable_device(pci_info->dev)) {
|
|
printk(KERN_ERR "failed to enable:"
|
|
"vendor %x, device %x, name %s\n",
|
|
PCI_VENDOR_ID_AMD, pci_info->err_dev,
|
|
pci_info->ctl_name);
|
|
goto err_dev_put;
|
|
}
|
|
|
|
/*
|
|
* we do not allocate extra private structure for
|
|
* edac_pci_ctl_info, but make use of existing
|
|
* one instead.
|
|
*/
|
|
pci_info->edac_idx = edac_pci_alloc_index();
|
|
pci_info->edac_dev = edac_pci_alloc_ctl_info(0, pci_info->ctl_name);
|
|
if (!pci_info->edac_dev) {
|
|
ret = -ENOMEM;
|
|
goto err_dev_put;
|
|
}
|
|
|
|
pci_info->edac_dev->pvt_info = pci_info;
|
|
pci_info->edac_dev->dev = &pci_info->dev->dev;
|
|
pci_info->edac_dev->mod_name = AMD8111_EDAC_MOD_STR;
|
|
pci_info->edac_dev->ctl_name = pci_info->ctl_name;
|
|
pci_info->edac_dev->dev_name = dev_name(&pci_info->dev->dev);
|
|
|
|
if (edac_op_state == EDAC_OPSTATE_POLL)
|
|
pci_info->edac_dev->edac_check = pci_info->check;
|
|
|
|
if (pci_info->init)
|
|
pci_info->init(pci_info);
|
|
|
|
if (edac_pci_add_device(pci_info->edac_dev, pci_info->edac_idx) > 0) {
|
|
printk(KERN_ERR "failed to add edac_pci for %s\n",
|
|
pci_info->ctl_name);
|
|
goto err_edac_free_ctl;
|
|
}
|
|
|
|
printk(KERN_INFO "added one edac_pci on AMD8111 "
|
|
"vendor %x, device %x, name %s\n",
|
|
PCI_VENDOR_ID_AMD, pci_info->err_dev,
|
|
pci_info->ctl_name);
|
|
|
|
return 0;
|
|
|
|
err_edac_free_ctl:
|
|
edac_pci_free_ctl_info(pci_info->edac_dev);
|
|
err_dev_put:
|
|
pci_dev_put(pci_info->dev);
|
|
err:
|
|
return ret;
|
|
}
|
|
|
|
static void amd8111_pci_remove(struct pci_dev *dev)
|
|
{
|
|
struct amd8111_pci_info *pci_info;
|
|
|
|
for (pci_info = amd8111_pcis; pci_info->err_dev; pci_info++)
|
|
if (pci_info->dev->device == dev->device)
|
|
break;
|
|
|
|
if (!pci_info->err_dev) /* should never happen */
|
|
return;
|
|
|
|
if (pci_info->edac_dev) {
|
|
edac_pci_del_device(pci_info->edac_dev->dev);
|
|
edac_pci_free_ctl_info(pci_info->edac_dev);
|
|
}
|
|
|
|
if (pci_info->exit)
|
|
pci_info->exit(pci_info);
|
|
|
|
pci_dev_put(pci_info->dev);
|
|
}
|
|
|
|
/* PCI Device ID talbe for general EDAC device */
|
|
static const struct pci_device_id amd8111_edac_dev_tbl[] = {
|
|
{
|
|
PCI_VEND_DEV(AMD, 8111_LPC),
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.class = 0,
|
|
.class_mask = 0,
|
|
.driver_data = LPC_BRIDGE,
|
|
},
|
|
{
|
|
0,
|
|
} /* table is NULL-terminated */
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, amd8111_edac_dev_tbl);
|
|
|
|
static struct pci_driver amd8111_edac_dev_driver = {
|
|
.name = "AMD8111_EDAC_DEV",
|
|
.probe = amd8111_dev_probe,
|
|
.remove = amd8111_dev_remove,
|
|
.id_table = amd8111_edac_dev_tbl,
|
|
};
|
|
|
|
/* PCI Device ID table for EDAC PCI controller */
|
|
static const struct pci_device_id amd8111_edac_pci_tbl[] = {
|
|
{
|
|
PCI_VEND_DEV(AMD, 8111_PCI),
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.class = 0,
|
|
.class_mask = 0,
|
|
.driver_data = PCI_BRIDGE,
|
|
},
|
|
{
|
|
0,
|
|
} /* table is NULL-terminated */
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, amd8111_edac_pci_tbl);
|
|
|
|
static struct pci_driver amd8111_edac_pci_driver = {
|
|
.name = "AMD8111_EDAC_PCI",
|
|
.probe = amd8111_pci_probe,
|
|
.remove = amd8111_pci_remove,
|
|
.id_table = amd8111_edac_pci_tbl,
|
|
};
|
|
|
|
static int __init amd8111_edac_init(void)
|
|
{
|
|
int val;
|
|
|
|
printk(KERN_INFO "AMD8111 EDAC driver " AMD8111_EDAC_REVISION "\n");
|
|
printk(KERN_INFO "\t(c) 2008 Wind River Systems, Inc.\n");
|
|
|
|
/* Only POLL mode supported so far */
|
|
edac_op_state = EDAC_OPSTATE_POLL;
|
|
|
|
val = pci_register_driver(&amd8111_edac_dev_driver);
|
|
val |= pci_register_driver(&amd8111_edac_pci_driver);
|
|
|
|
return val;
|
|
}
|
|
|
|
static void __exit amd8111_edac_exit(void)
|
|
{
|
|
pci_unregister_driver(&amd8111_edac_pci_driver);
|
|
pci_unregister_driver(&amd8111_edac_dev_driver);
|
|
}
|
|
|
|
|
|
module_init(amd8111_edac_init);
|
|
module_exit(amd8111_edac_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Cao Qingtao <qingtao.cao@windriver.com>\n");
|
|
MODULE_DESCRIPTION("AMD8111 HyperTransport I/O Hub EDAC kernel module");
|