230 lines
6.2 KiB
C
230 lines
6.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2022 Intel Corporation. All rights reserved. */
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include "cxlmem.h"
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#include "cxlpci.h"
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/**
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* DOC: cxl mem
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*
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* CXL memory endpoint devices and switches are CXL capable devices that are
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* participating in CXL.mem protocol. Their functionality builds on top of the
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* CXL.io protocol that allows enumerating and configuring components via
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* standard PCI mechanisms.
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*
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* The cxl_mem driver owns kicking off the enumeration of this CXL.mem
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* capability. With the detection of a CXL capable endpoint, the driver will
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* walk up to find the platform specific port it is connected to, and determine
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* if there are intervening switches in the path. If there are switches, a
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* secondary action is to enumerate those (implemented in cxl_core). Finally the
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* cxl_mem driver adds the device it is bound to as a CXL endpoint-port for use
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* in higher level operations.
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*/
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static int wait_for_media(struct cxl_memdev *cxlmd)
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{
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struct cxl_dev_state *cxlds = cxlmd->cxlds;
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int rc;
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rc = cxlds->wait_media_ready(cxlds);
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if (rc)
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return rc;
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/*
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* We know the device is active, and enabled, if any ranges are non-zero
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* we'll need to check later before adding the port since that owns the
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* HDM decoder registers.
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*/
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return 0;
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}
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static int create_endpoint(struct cxl_memdev *cxlmd,
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struct cxl_port *parent_port)
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{
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struct cxl_dev_state *cxlds = cxlmd->cxlds;
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struct cxl_port *endpoint;
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int rc;
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endpoint = devm_cxl_add_port(&parent_port->dev, &cxlmd->dev,
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cxlds->component_reg_phys, parent_port);
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if (IS_ERR(endpoint))
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return PTR_ERR(endpoint);
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dev_dbg(&cxlmd->dev, "add: %s\n", dev_name(&endpoint->dev));
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rc = cxl_endpoint_autoremove(cxlmd, endpoint);
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if (rc)
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return rc;
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if (!endpoint->dev.driver) {
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dev_err(&cxlmd->dev, "%s failed probe\n",
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dev_name(&endpoint->dev));
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return -ENXIO;
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}
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return 0;
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}
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/**
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* cxl_dvsec_decode_init() - Setup HDM decoding for the endpoint
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* @cxlds: Device state
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*
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* Additionally, enables global HDM decoding. Warning: don't call this outside
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* of probe. Once probe is complete, the port driver owns all access to the HDM
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* decoder registers.
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*
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* Returns: false if DVSEC Ranges are being used instead of HDM
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* decoders, or if it can not be determined if DVSEC Ranges are in use.
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* Otherwise, returns true.
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*/
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__mock bool cxl_dvsec_decode_init(struct cxl_dev_state *cxlds)
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{
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struct cxl_endpoint_dvsec_info *info = &cxlds->info;
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struct cxl_register_map map;
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struct cxl_component_reg_map *cmap = &map.component_map;
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bool global_enable, do_hdm_init = false;
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void __iomem *crb;
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u32 global_ctrl;
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/* map hdm decoder */
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crb = ioremap(cxlds->component_reg_phys, CXL_COMPONENT_REG_BLOCK_SIZE);
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if (!crb) {
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dev_dbg(cxlds->dev, "Failed to map component registers\n");
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return false;
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}
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cxl_probe_component_regs(cxlds->dev, crb, cmap);
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if (!cmap->hdm_decoder.valid) {
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dev_dbg(cxlds->dev, "Invalid HDM decoder registers\n");
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goto out;
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}
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global_ctrl = readl(crb + cmap->hdm_decoder.offset +
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CXL_HDM_DECODER_CTRL_OFFSET);
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global_enable = global_ctrl & CXL_HDM_DECODER_ENABLE;
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if (!global_enable && info->ranges) {
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dev_dbg(cxlds->dev,
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"DVSEC ranges already programmed and HDM decoders not enabled.\n");
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goto out;
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}
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do_hdm_init = true;
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/*
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* Permanently (for this boot at least) opt the device into HDM
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* operation. Individual HDM decoders still need to be enabled after
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* this point.
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*/
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if (!global_enable) {
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dev_dbg(cxlds->dev, "Enabling HDM decode\n");
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writel(global_ctrl | CXL_HDM_DECODER_ENABLE,
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crb + cmap->hdm_decoder.offset +
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CXL_HDM_DECODER_CTRL_OFFSET);
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}
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out:
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iounmap(crb);
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return do_hdm_init;
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}
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static int cxl_mem_probe(struct device *dev)
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{
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struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
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struct cxl_dev_state *cxlds = cxlmd->cxlds;
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struct cxl_port *parent_port;
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int rc;
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/*
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* Someone is trying to reattach this device after it lost its port
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* connection (an endpoint port previously registered by this memdev was
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* disabled). This racy check is ok because if the port is still gone,
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* no harm done, and if the port hierarchy comes back it will re-trigger
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* this probe. Port rescan and memdev detach work share the same
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* single-threaded workqueue.
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*/
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if (work_pending(&cxlmd->detach_work))
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return -EBUSY;
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rc = wait_for_media(cxlmd);
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if (rc) {
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dev_err(dev, "Media not active (%d)\n", rc);
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return rc;
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}
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/*
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* If DVSEC ranges are being used instead of HDM decoder registers there
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* is no use in trying to manage those.
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*/
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if (!cxl_dvsec_decode_init(cxlds)) {
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struct cxl_endpoint_dvsec_info *info = &cxlds->info;
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int i;
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/* */
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for (i = 0; i < 2; i++) {
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u64 base, size;
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/*
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* Give a nice warning to the user that BIOS has really
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* botched things for them if it didn't place DVSEC
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* ranges in the memory map.
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*/
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base = info->dvsec_range[i].start;
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size = range_len(&info->dvsec_range[i]);
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if (size && !region_intersects(base, size,
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IORESOURCE_SYSTEM_RAM,
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IORES_DESC_NONE)) {
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dev_err(dev,
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"DVSEC range %#llx-%#llx must be reserved by BIOS, but isn't\n",
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base, base + size - 1);
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}
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}
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dev_err(dev,
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"Active DVSEC range registers in use. Will not bind.\n");
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return -EBUSY;
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}
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rc = devm_cxl_enumerate_ports(cxlmd);
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if (rc)
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return rc;
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parent_port = cxl_mem_find_port(cxlmd);
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if (!parent_port) {
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dev_err(dev, "CXL port topology not found\n");
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return -ENXIO;
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}
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cxl_device_lock(&parent_port->dev);
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if (!parent_port->dev.driver) {
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dev_err(dev, "CXL port topology %s not enabled\n",
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dev_name(&parent_port->dev));
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rc = -ENXIO;
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goto out;
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}
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rc = create_endpoint(cxlmd, parent_port);
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out:
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cxl_device_unlock(&parent_port->dev);
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put_device(&parent_port->dev);
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return rc;
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}
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static struct cxl_driver cxl_mem_driver = {
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.name = "cxl_mem",
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.probe = cxl_mem_probe,
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.id = CXL_DEVICE_MEMORY_EXPANDER,
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};
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module_cxl_driver(cxl_mem_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_IMPORT_NS(CXL);
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MODULE_ALIAS_CXL(CXL_DEVICE_MEMORY_EXPANDER);
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/*
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* create_endpoint() wants to validate port driver attach immediately after
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* endpoint registration.
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*/
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MODULE_SOFTDEP("pre: cxl_port");
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