307 lines
10 KiB
C
307 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright(c) 2020-2021 Intel Corporation. */
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#ifndef __CXL_MEM_H__
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#define __CXL_MEM_H__
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#include <uapi/linux/cxl_mem.h>
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#include <linux/cdev.h>
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#include "cxl.h"
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/* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */
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#define CXLMDEV_STATUS_OFFSET 0x0
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#define CXLMDEV_DEV_FATAL BIT(0)
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#define CXLMDEV_FW_HALT BIT(1)
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#define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2)
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#define CXLMDEV_MS_NOT_READY 0
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#define CXLMDEV_MS_READY 1
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#define CXLMDEV_MS_ERROR 2
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#define CXLMDEV_MS_DISABLED 3
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#define CXLMDEV_READY(status) \
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(FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \
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CXLMDEV_MS_READY)
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#define CXLMDEV_MBOX_IF_READY BIT(4)
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#define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5)
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#define CXLMDEV_RESET_NEEDED_NOT 0
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#define CXLMDEV_RESET_NEEDED_COLD 1
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#define CXLMDEV_RESET_NEEDED_WARM 2
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#define CXLMDEV_RESET_NEEDED_HOT 3
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#define CXLMDEV_RESET_NEEDED_CXL 4
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#define CXLMDEV_RESET_NEEDED(status) \
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(FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \
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CXLMDEV_RESET_NEEDED_NOT)
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/**
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* struct cxl_memdev - CXL bus object representing a Type-3 Memory Device
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* @dev: driver core device object
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* @cdev: char dev core object for ioctl operations
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* @cxlds: The device state backing this device
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* @detach_work: active memdev lost a port in its ancestry
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* @id: id number of this memdev instance.
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*/
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struct cxl_memdev {
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struct device dev;
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struct cdev cdev;
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struct cxl_dev_state *cxlds;
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struct work_struct detach_work;
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int id;
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};
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static inline struct cxl_memdev *to_cxl_memdev(struct device *dev)
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{
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return container_of(dev, struct cxl_memdev, dev);
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}
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bool is_cxl_memdev(struct device *dev);
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static inline bool is_cxl_endpoint(struct cxl_port *port)
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{
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return is_cxl_memdev(port->uport);
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}
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struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds);
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/**
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* struct cxl_mbox_cmd - A command to be submitted to hardware.
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* @opcode: (input) The command set and command submitted to hardware.
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* @payload_in: (input) Pointer to the input payload.
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* @payload_out: (output) Pointer to the output payload. Must be allocated by
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* the caller.
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* @size_in: (input) Number of bytes to load from @payload_in.
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* @size_out: (input) Max number of bytes loaded into @payload_out.
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* (output) Number of bytes generated by the device. For fixed size
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* outputs commands this is always expected to be deterministic. For
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* variable sized output commands, it tells the exact number of bytes
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* written.
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* @return_code: (output) Error code returned from hardware.
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*
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* This is the primary mechanism used to send commands to the hardware.
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* All the fields except @payload_* correspond exactly to the fields described in
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* Command Register section of the CXL 2.0 8.2.8.4.5. @payload_in and
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* @payload_out are written to, and read from the Command Payload Registers
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* defined in CXL 2.0 8.2.8.4.8.
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*/
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struct cxl_mbox_cmd {
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u16 opcode;
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void *payload_in;
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void *payload_out;
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size_t size_in;
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size_t size_out;
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u16 return_code;
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#define CXL_MBOX_SUCCESS 0
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};
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/*
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* CXL 2.0 - Memory capacity multiplier
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* See Section 8.2.9.5
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*
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* Volatile, Persistent, and Partition capacities are specified to be in
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* multiples of 256MB - define a multiplier to convert to/from bytes.
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*/
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#define CXL_CAPACITY_MULTIPLIER SZ_256M
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/**
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* struct cxl_endpoint_dvsec_info - Cached DVSEC info
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* @mem_enabled: cached value of mem_enabled in the DVSEC, PCIE_DEVICE
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* @ranges: Number of active HDM ranges this device uses.
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* @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE
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*/
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struct cxl_endpoint_dvsec_info {
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bool mem_enabled;
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int ranges;
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struct range dvsec_range[2];
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};
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/**
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* struct cxl_dev_state - The driver device state
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*
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* cxl_dev_state represents the CXL driver/device state. It provides an
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* interface to mailbox commands as well as some cached data about the device.
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* Currently only memory devices are represented.
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*
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* @dev: The device associated with this CXL state
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* @regs: Parsed register blocks
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* @cxl_dvsec: Offset to the PCIe device DVSEC
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* @payload_size: Size of space for payload
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* (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register)
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* @lsa_size: Size of Label Storage Area
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* (CXL 2.0 8.2.9.5.1.1 Identify Memory Device)
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* @mbox_mutex: Mutex to synchronize mailbox access.
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* @firmware_version: Firmware version for the memory device.
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* @enabled_cmds: Hardware commands found enabled in CEL.
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* @exclusive_cmds: Commands that are kernel-internal only
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* @pmem_range: Active Persistent memory capacity configuration
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* @ram_range: Active Volatile memory capacity configuration
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* @total_bytes: sum of all possible capacities
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* @volatile_only_bytes: hard volatile capacity
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* @persistent_only_bytes: hard persistent capacity
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* @partition_align_bytes: alignment size for partition-able capacity
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* @active_volatile_bytes: sum of hard + soft volatile
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* @active_persistent_bytes: sum of hard + soft persistent
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* @next_volatile_bytes: volatile capacity change pending device reset
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* @next_persistent_bytes: persistent capacity change pending device reset
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* @component_reg_phys: register base of component registers
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* @info: Cached DVSEC information about the device.
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* @serial: PCIe Device Serial Number
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* @mbox_send: @dev specific transport for transmitting mailbox commands
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* @wait_media_ready: @dev specific method to await media ready
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*
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* See section 8.2.9.5.2 Capacity Configuration and Label Storage for
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* details on capacity parameters.
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*/
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struct cxl_dev_state {
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struct device *dev;
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struct cxl_regs regs;
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int cxl_dvsec;
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size_t payload_size;
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size_t lsa_size;
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struct mutex mbox_mutex; /* Protects device mailbox and firmware */
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char firmware_version[0x10];
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DECLARE_BITMAP(enabled_cmds, CXL_MEM_COMMAND_ID_MAX);
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DECLARE_BITMAP(exclusive_cmds, CXL_MEM_COMMAND_ID_MAX);
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struct range pmem_range;
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struct range ram_range;
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u64 total_bytes;
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u64 volatile_only_bytes;
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u64 persistent_only_bytes;
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u64 partition_align_bytes;
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u64 active_volatile_bytes;
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u64 active_persistent_bytes;
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u64 next_volatile_bytes;
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u64 next_persistent_bytes;
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resource_size_t component_reg_phys;
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struct cxl_endpoint_dvsec_info info;
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u64 serial;
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int (*mbox_send)(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd);
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int (*wait_media_ready)(struct cxl_dev_state *cxlds);
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};
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enum cxl_opcode {
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CXL_MBOX_OP_INVALID = 0x0000,
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CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID,
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CXL_MBOX_OP_GET_FW_INFO = 0x0200,
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CXL_MBOX_OP_ACTIVATE_FW = 0x0202,
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CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400,
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CXL_MBOX_OP_GET_LOG = 0x0401,
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CXL_MBOX_OP_IDENTIFY = 0x4000,
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CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100,
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CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101,
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CXL_MBOX_OP_GET_LSA = 0x4102,
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CXL_MBOX_OP_SET_LSA = 0x4103,
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CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200,
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CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201,
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CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202,
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CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203,
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CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204,
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CXL_MBOX_OP_GET_POISON = 0x4300,
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CXL_MBOX_OP_INJECT_POISON = 0x4301,
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CXL_MBOX_OP_CLEAR_POISON = 0x4302,
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CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303,
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CXL_MBOX_OP_SCAN_MEDIA = 0x4304,
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CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305,
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CXL_MBOX_OP_MAX = 0x10000
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};
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#define DEFINE_CXL_CEL_UUID \
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UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62, \
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0x3b, 0x3f, 0x17)
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#define DEFINE_CXL_VENDOR_DEBUG_UUID \
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UUID_INIT(0xe1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \
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0x40, 0x3d, 0x86)
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struct cxl_mbox_get_supported_logs {
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__le16 entries;
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u8 rsvd[6];
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struct cxl_gsl_entry {
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uuid_t uuid;
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__le32 size;
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} __packed entry[];
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} __packed;
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struct cxl_cel_entry {
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__le16 opcode;
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__le16 effect;
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} __packed;
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struct cxl_mbox_get_log {
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uuid_t uuid;
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__le32 offset;
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__le32 length;
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} __packed;
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/* See CXL 2.0 Table 175 Identify Memory Device Output Payload */
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struct cxl_mbox_identify {
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char fw_revision[0x10];
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__le64 total_capacity;
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__le64 volatile_capacity;
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__le64 persistent_capacity;
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__le64 partition_align;
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__le16 info_event_log_size;
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__le16 warning_event_log_size;
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__le16 failure_event_log_size;
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__le16 fatal_event_log_size;
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__le32 lsa_size;
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u8 poison_list_max_mer[3];
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__le16 inject_poison_limit;
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u8 poison_caps;
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u8 qos_telemetry_caps;
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} __packed;
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struct cxl_mbox_get_lsa {
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__le32 offset;
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__le32 length;
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} __packed;
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struct cxl_mbox_set_lsa {
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__le32 offset;
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__le32 reserved;
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u8 data[];
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} __packed;
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/**
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* struct cxl_mem_command - Driver representation of a memory device command
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* @info: Command information as it exists for the UAPI
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* @opcode: The actual bits used for the mailbox protocol
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* @flags: Set of flags effecting driver behavior.
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*
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* * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag
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* will be enabled by the driver regardless of what hardware may have
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* advertised.
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*
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* The cxl_mem_command is the driver's internal representation of commands that
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* are supported by the driver. Some of these commands may not be supported by
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* the hardware. The driver will use @info to validate the fields passed in by
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* the user then submit the @opcode to the hardware.
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*
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* See struct cxl_command_info.
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*/
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struct cxl_mem_command {
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struct cxl_command_info info;
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enum cxl_opcode opcode;
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u32 flags;
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#define CXL_CMD_FLAG_NONE 0
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#define CXL_CMD_FLAG_FORCE_ENABLE BIT(0)
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};
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int cxl_mbox_send_cmd(struct cxl_dev_state *cxlds, u16 opcode, void *in,
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size_t in_size, void *out, size_t out_size);
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int cxl_dev_state_identify(struct cxl_dev_state *cxlds);
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int cxl_enumerate_cmds(struct cxl_dev_state *cxlds);
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int cxl_mem_create_range_info(struct cxl_dev_state *cxlds);
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struct cxl_dev_state *cxl_dev_state_create(struct device *dev);
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void set_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds);
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void clear_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds);
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struct cxl_hdm {
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struct cxl_component_regs regs;
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unsigned int decoder_count;
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unsigned int target_count;
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unsigned int interleave_mask;
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struct cxl_port *port;
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};
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#endif /* __CXL_MEM_H__ */
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