634 lines
17 KiB
C
634 lines
17 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
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#ifndef __CC_HW_QUEUE_DEFS_H__
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#define __CC_HW_QUEUE_DEFS_H__
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#include <linux/types.h>
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#include "cc_kernel_regs.h"
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#include <linux/bitfield.h>
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/******************************************************************************
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* DEFINITIONS
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******************************************************************************/
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#define HW_DESC_SIZE_WORDS 6
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/* Define max. available slots in HW queue */
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#define HW_QUEUE_SLOTS_MAX 15
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#define CC_REG_LOW(name) (name ## _BIT_SHIFT)
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#define CC_REG_HIGH(name) (CC_REG_LOW(name) + name ## _BIT_SIZE - 1)
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#define CC_GENMASK(name) GENMASK(CC_REG_HIGH(name), CC_REG_LOW(name))
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#define CC_HWQ_GENMASK(word, field) \
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CC_GENMASK(CC_DSCRPTR_QUEUE_WORD ## word ## _ ## field)
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#define WORD0_VALUE CC_HWQ_GENMASK(0, VALUE)
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#define WORD0_CPP_CIPHER_MODE CC_HWQ_GENMASK(0, CPP_CIPHER_MODE)
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#define WORD1_DIN_CONST_VALUE CC_HWQ_GENMASK(1, DIN_CONST_VALUE)
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#define WORD1_DIN_DMA_MODE CC_HWQ_GENMASK(1, DIN_DMA_MODE)
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#define WORD1_DIN_SIZE CC_HWQ_GENMASK(1, DIN_SIZE)
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#define WORD1_NOT_LAST CC_HWQ_GENMASK(1, NOT_LAST)
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#define WORD1_NS_BIT CC_HWQ_GENMASK(1, NS_BIT)
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#define WORD1_LOCK_QUEUE CC_HWQ_GENMASK(1, LOCK_QUEUE)
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#define WORD2_VALUE CC_HWQ_GENMASK(2, VALUE)
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#define WORD3_DOUT_DMA_MODE CC_HWQ_GENMASK(3, DOUT_DMA_MODE)
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#define WORD3_DOUT_LAST_IND CC_HWQ_GENMASK(3, DOUT_LAST_IND)
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#define WORD3_DOUT_SIZE CC_HWQ_GENMASK(3, DOUT_SIZE)
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#define WORD3_HASH_XOR_BIT CC_HWQ_GENMASK(3, HASH_XOR_BIT)
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#define WORD3_NS_BIT CC_HWQ_GENMASK(3, NS_BIT)
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#define WORD3_QUEUE_LAST_IND CC_HWQ_GENMASK(3, QUEUE_LAST_IND)
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#define WORD4_ACK_NEEDED CC_HWQ_GENMASK(4, ACK_NEEDED)
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#define WORD4_AES_SEL_N_HASH CC_HWQ_GENMASK(4, AES_SEL_N_HASH)
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#define WORD4_AES_XOR_CRYPTO_KEY CC_HWQ_GENMASK(4, AES_XOR_CRYPTO_KEY)
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#define WORD4_BYTES_SWAP CC_HWQ_GENMASK(4, BYTES_SWAP)
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#define WORD4_CIPHER_CONF0 CC_HWQ_GENMASK(4, CIPHER_CONF0)
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#define WORD4_CIPHER_CONF1 CC_HWQ_GENMASK(4, CIPHER_CONF1)
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#define WORD4_CIPHER_CONF2 CC_HWQ_GENMASK(4, CIPHER_CONF2)
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#define WORD4_CIPHER_DO CC_HWQ_GENMASK(4, CIPHER_DO)
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#define WORD4_CIPHER_MODE CC_HWQ_GENMASK(4, CIPHER_MODE)
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#define WORD4_CMAC_SIZE0 CC_HWQ_GENMASK(4, CMAC_SIZE0)
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#define WORD4_DATA_FLOW_MODE CC_HWQ_GENMASK(4, DATA_FLOW_MODE)
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#define WORD4_KEY_SIZE CC_HWQ_GENMASK(4, KEY_SIZE)
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#define WORD4_SETUP_OPERATION CC_HWQ_GENMASK(4, SETUP_OPERATION)
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#define WORD5_DIN_ADDR_HIGH CC_HWQ_GENMASK(5, DIN_ADDR_HIGH)
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#define WORD5_DOUT_ADDR_HIGH CC_HWQ_GENMASK(5, DOUT_ADDR_HIGH)
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/******************************************************************************
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* TYPE DEFINITIONS
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******************************************************************************/
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struct cc_hw_desc {
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union {
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u32 word[HW_DESC_SIZE_WORDS];
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u16 hword[HW_DESC_SIZE_WORDS * 2];
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};
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};
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enum cc_axi_sec {
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AXI_SECURE = 0,
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AXI_NOT_SECURE = 1
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};
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enum cc_desc_direction {
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DESC_DIRECTION_ILLEGAL = -1,
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DESC_DIRECTION_ENCRYPT_ENCRYPT = 0,
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DESC_DIRECTION_DECRYPT_DECRYPT = 1,
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DESC_DIRECTION_DECRYPT_ENCRYPT = 3,
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DESC_DIRECTION_END = S32_MAX,
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};
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enum cc_dma_mode {
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DMA_MODE_NULL = -1,
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NO_DMA = 0,
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DMA_SRAM = 1,
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DMA_DLLI = 2,
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DMA_MLLI = 3,
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DMA_MODE_END = S32_MAX,
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};
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enum cc_flow_mode {
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FLOW_MODE_NULL = -1,
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/* data flows */
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BYPASS = 0,
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DIN_AES_DOUT = 1,
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AES_to_HASH = 2,
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AES_and_HASH = 3,
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DIN_DES_DOUT = 4,
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DES_to_HASH = 5,
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DES_and_HASH = 6,
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DIN_HASH = 7,
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DIN_HASH_and_BYPASS = 8,
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AESMAC_and_BYPASS = 9,
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AES_to_HASH_and_DOUT = 10,
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DIN_RC4_DOUT = 11,
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DES_to_HASH_and_DOUT = 12,
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AES_to_AES_to_HASH_and_DOUT = 13,
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AES_to_AES_to_HASH = 14,
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AES_to_HASH_and_AES = 15,
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DIN_SM4_DOUT = 16,
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DIN_AES_AESMAC = 17,
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HASH_to_DOUT = 18,
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/* setup flows */
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S_DIN_to_AES = 32,
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S_DIN_to_AES2 = 33,
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S_DIN_to_DES = 34,
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S_DIN_to_RC4 = 35,
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S_DIN_to_SM4 = 36,
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S_DIN_to_HASH = 37,
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S_AES_to_DOUT = 38,
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S_AES2_to_DOUT = 39,
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S_SM4_to_DOUT = 40,
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S_RC4_to_DOUT = 41,
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S_DES_to_DOUT = 42,
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S_HASH_to_DOUT = 43,
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SET_FLOW_ID = 44,
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FLOW_MODE_END = S32_MAX,
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};
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enum cc_setup_op {
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SETUP_LOAD_NOP = 0,
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SETUP_LOAD_STATE0 = 1,
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SETUP_LOAD_STATE1 = 2,
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SETUP_LOAD_STATE2 = 3,
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SETUP_LOAD_KEY0 = 4,
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SETUP_LOAD_XEX_KEY = 5,
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SETUP_WRITE_STATE0 = 8,
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SETUP_WRITE_STATE1 = 9,
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SETUP_WRITE_STATE2 = 10,
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SETUP_WRITE_STATE3 = 11,
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SETUP_OP_END = S32_MAX,
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};
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enum cc_hash_conf_pad {
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HASH_PADDING_DISABLED = 0,
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HASH_PADDING_ENABLED = 1,
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HASH_DIGEST_RESULT_LITTLE_ENDIAN = 2,
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HASH_CONFIG1_PADDING_RESERVE32 = S32_MAX,
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};
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enum cc_aes_mac_selector {
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AES_SK = 1,
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AES_CMAC_INIT = 2,
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AES_CMAC_SIZE0 = 3,
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AES_MAC_END = S32_MAX,
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};
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#define HW_KEY_MASK_CIPHER_DO 0x3
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#define HW_KEY_SHIFT_CIPHER_CFG2 2
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/* HwCryptoKey[1:0] is mapped to cipher_do[1:0] */
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/* HwCryptoKey[2:3] is mapped to cipher_config2[1:0] */
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enum cc_hw_crypto_key {
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USER_KEY = 0, /* 0x0000 */
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ROOT_KEY = 1, /* 0x0001 */
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PROVISIONING_KEY = 2, /* 0x0010 */ /* ==KCP */
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SESSION_KEY = 3, /* 0x0011 */
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RESERVED_KEY = 4, /* NA */
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PLATFORM_KEY = 5, /* 0x0101 */
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CUSTOMER_KEY = 6, /* 0x0110 */
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KFDE0_KEY = 7, /* 0x0111 */
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KFDE1_KEY = 9, /* 0x1001 */
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KFDE2_KEY = 10, /* 0x1010 */
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KFDE3_KEY = 11, /* 0x1011 */
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END_OF_KEYS = S32_MAX,
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};
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#define CC_NUM_HW_KEY_SLOTS 4
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#define CC_FIRST_HW_KEY_SLOT 0
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#define CC_LAST_HW_KEY_SLOT (CC_FIRST_HW_KEY_SLOT + CC_NUM_HW_KEY_SLOTS - 1)
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#define CC_NUM_CPP_KEY_SLOTS 8
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#define CC_FIRST_CPP_KEY_SLOT 16
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#define CC_LAST_CPP_KEY_SLOT (CC_FIRST_CPP_KEY_SLOT + \
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CC_NUM_CPP_KEY_SLOTS - 1)
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enum cc_hw_aes_key_size {
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AES_128_KEY = 0,
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AES_192_KEY = 1,
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AES_256_KEY = 2,
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END_OF_AES_KEYS = S32_MAX,
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};
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enum cc_hash_cipher_pad {
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DO_NOT_PAD = 0,
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DO_PAD = 1,
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HASH_CIPHER_DO_PADDING_RESERVE32 = S32_MAX,
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};
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#define CC_CPP_DIN_ADDR 0xFF00FF00UL
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#define CC_CPP_DIN_SIZE 0xFF00FFUL
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/*****************************/
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/* Descriptor packing macros */
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/*****************************/
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/**
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* hw_desc_init() - Init a HW descriptor struct
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* @pdesc: pointer to HW descriptor struct
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*/
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static inline void hw_desc_init(struct cc_hw_desc *pdesc)
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{
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memset(pdesc, 0, sizeof(struct cc_hw_desc));
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}
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/**
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* set_queue_last_ind_bit() - Indicate the end of current HW descriptors flow
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* and release the HW engines.
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*
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* @pdesc: Pointer to HW descriptor struct
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*/
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static inline void set_queue_last_ind_bit(struct cc_hw_desc *pdesc)
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{
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pdesc->word[3] |= FIELD_PREP(WORD3_QUEUE_LAST_IND, 1);
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}
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/**
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* set_din_type() - Set the DIN field of a HW descriptor
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*
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* @pdesc: Pointer to HW descriptor struct
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* @dma_mode: The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT
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* @addr: DIN address
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* @size: Data size in bytes
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* @axi_sec: AXI secure bit
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*/
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static inline void set_din_type(struct cc_hw_desc *pdesc,
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enum cc_dma_mode dma_mode, dma_addr_t addr,
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u32 size, enum cc_axi_sec axi_sec)
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{
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pdesc->word[0] = lower_32_bits(addr);
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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pdesc->word[5] |= FIELD_PREP(WORD5_DIN_ADDR_HIGH, upper_32_bits(addr));
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#endif
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pdesc->word[1] |= FIELD_PREP(WORD1_DIN_DMA_MODE, dma_mode) |
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FIELD_PREP(WORD1_DIN_SIZE, size) |
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FIELD_PREP(WORD1_NS_BIT, axi_sec);
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}
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/**
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* set_din_no_dma() - Set the DIN field of a HW descriptor to NO DMA mode.
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* Used for NOP descriptor, register patches and other special modes.
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*
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* @pdesc: Pointer to HW descriptor struct
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* @addr: DIN address
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* @size: Data size in bytes
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*/
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static inline void set_din_no_dma(struct cc_hw_desc *pdesc, u32 addr, u32 size)
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{
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pdesc->word[0] = addr;
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pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size);
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}
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/**
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* set_cpp_crypto_key() - Setup the special CPP descriptor
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*
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* @pdesc: Pointer to HW descriptor struct
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* @slot: Slot number
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*/
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static inline void set_cpp_crypto_key(struct cc_hw_desc *pdesc, u8 slot)
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{
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pdesc->word[0] |= CC_CPP_DIN_ADDR;
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pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, CC_CPP_DIN_SIZE);
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pdesc->word[1] |= FIELD_PREP(WORD1_LOCK_QUEUE, 1);
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pdesc->word[4] |= FIELD_PREP(WORD4_SETUP_OPERATION, slot);
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}
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/**
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* set_din_sram() - Set the DIN field of a HW descriptor to SRAM mode.
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* Note: No need to check SRAM alignment since host requests do not use SRAM and
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* the adaptor will enforce alignment checks.
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*
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* @pdesc: Pointer to HW descriptor struct
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* @addr: DIN address
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* @size: Data size in bytes
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*/
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static inline void set_din_sram(struct cc_hw_desc *pdesc, u32 addr, u32 size)
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{
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pdesc->word[0] = addr;
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pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size) |
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FIELD_PREP(WORD1_DIN_DMA_MODE, DMA_SRAM);
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}
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/**
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* set_din_const() - Set the DIN field of a HW descriptor to CONST mode
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*
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* @pdesc: Pointer to HW descriptor struct
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* @val: DIN const value
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* @size: Data size in bytes
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*/
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static inline void set_din_const(struct cc_hw_desc *pdesc, u32 val, u32 size)
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{
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pdesc->word[0] = val;
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pdesc->word[1] |= FIELD_PREP(WORD1_DIN_CONST_VALUE, 1) |
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FIELD_PREP(WORD1_DIN_DMA_MODE, DMA_SRAM) |
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FIELD_PREP(WORD1_DIN_SIZE, size);
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}
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/**
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* set_din_not_last_indication() - Set the DIN not last input data indicator
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*
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* @pdesc: Pointer to HW descriptor struct
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*/
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static inline void set_din_not_last_indication(struct cc_hw_desc *pdesc)
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{
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pdesc->word[1] |= FIELD_PREP(WORD1_NOT_LAST, 1);
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}
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/**
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* set_dout_type() - Set the DOUT field of a HW descriptor
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*
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* @pdesc: Pointer to HW descriptor struct
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* @dma_mode: The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT
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* @addr: DOUT address
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* @size: Data size in bytes
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* @axi_sec: AXI secure bit
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*/
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static inline void set_dout_type(struct cc_hw_desc *pdesc,
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enum cc_dma_mode dma_mode, dma_addr_t addr,
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u32 size, enum cc_axi_sec axi_sec)
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{
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pdesc->word[2] = lower_32_bits(addr);
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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pdesc->word[5] |= FIELD_PREP(WORD5_DOUT_ADDR_HIGH, upper_32_bits(addr));
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#endif
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pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_DMA_MODE, dma_mode) |
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FIELD_PREP(WORD3_DOUT_SIZE, size) |
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FIELD_PREP(WORD3_NS_BIT, axi_sec);
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}
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/**
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* set_dout_dlli() - Set the DOUT field of a HW descriptor to DLLI type
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* The LAST INDICATION is provided by the user
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*
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* @pdesc: Pointer to HW descriptor struct
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* @addr: DOUT address
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* @size: Data size in bytes
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* @axi_sec: AXI secure bit
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* @last_ind: The last indication bit
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*/
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static inline void set_dout_dlli(struct cc_hw_desc *pdesc, dma_addr_t addr,
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u32 size, enum cc_axi_sec axi_sec,
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u32 last_ind)
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{
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set_dout_type(pdesc, DMA_DLLI, addr, size, axi_sec);
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pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_LAST_IND, last_ind);
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}
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/**
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* set_dout_mlli() - Set the DOUT field of a HW descriptor to MLLI type
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* The LAST INDICATION is provided by the user
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*
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* @pdesc: Pointer to HW descriptor struct
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* @addr: DOUT address
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* @size: Data size in bytes
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* @axi_sec: AXI secure bit
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* @last_ind: The last indication bit
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*/
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static inline void set_dout_mlli(struct cc_hw_desc *pdesc, u32 addr, u32 size,
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enum cc_axi_sec axi_sec, bool last_ind)
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{
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set_dout_type(pdesc, DMA_MLLI, addr, size, axi_sec);
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pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_LAST_IND, last_ind);
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}
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/**
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* set_dout_no_dma() - Set the DOUT field of a HW descriptor to NO DMA mode.
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* Used for NOP descriptor, register patches and other special modes.
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*
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* @pdesc: pointer to HW descriptor struct
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* @addr: DOUT address
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* @size: Data size in bytes
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* @write_enable: Enables a write operation to a register
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*/
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static inline void set_dout_no_dma(struct cc_hw_desc *pdesc, u32 addr,
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u32 size, bool write_enable)
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{
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pdesc->word[2] = addr;
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pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_SIZE, size) |
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FIELD_PREP(WORD3_DOUT_LAST_IND, write_enable);
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}
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/**
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* set_xor_val() - Set the word for the XOR operation.
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*
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* @pdesc: Pointer to HW descriptor struct
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* @val: XOR data value
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*/
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static inline void set_xor_val(struct cc_hw_desc *pdesc, u32 val)
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{
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pdesc->word[2] = val;
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}
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/**
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* set_xor_active() - Set the XOR indicator bit in the descriptor
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*
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* @pdesc: Pointer to HW descriptor struct
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*/
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static inline void set_xor_active(struct cc_hw_desc *pdesc)
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{
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pdesc->word[3] |= FIELD_PREP(WORD3_HASH_XOR_BIT, 1);
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}
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/**
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* set_aes_not_hash_mode() - Select the AES engine instead of HASH engine when
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* setting up combined mode with AES XCBC MAC
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*
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* @pdesc: Pointer to HW descriptor struct
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*/
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static inline void set_aes_not_hash_mode(struct cc_hw_desc *pdesc)
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{
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pdesc->word[4] |= FIELD_PREP(WORD4_AES_SEL_N_HASH, 1);
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}
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/**
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* set_aes_xor_crypto_key() - Set aes xor crypto key, which in some scenarios
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* selects the SM3 engine
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*
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* @pdesc: Pointer to HW descriptor struct
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*/
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static inline void set_aes_xor_crypto_key(struct cc_hw_desc *pdesc)
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{
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pdesc->word[4] |= FIELD_PREP(WORD4_AES_XOR_CRYPTO_KEY, 1);
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}
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/**
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* set_dout_sram() - Set the DOUT field of a HW descriptor to SRAM mode
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* Note: No need to check SRAM alignment since host requests do not use SRAM and
|
|
* the adaptor will enforce alignment checks.
|
|
*
|
|
* @pdesc: Pointer to HW descriptor struct
|
|
* @addr: DOUT address
|
|
* @size: Data size in bytes
|
|
*/
|
|
static inline void set_dout_sram(struct cc_hw_desc *pdesc, u32 addr, u32 size)
|
|
{
|
|
pdesc->word[2] = addr;
|
|
pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_DMA_MODE, DMA_SRAM) |
|
|
FIELD_PREP(WORD3_DOUT_SIZE, size);
|
|
}
|
|
|
|
/**
|
|
* set_xex_data_unit_size() - Set the data unit size for XEX mode in
|
|
* data_out_addr[15:0]
|
|
*
|
|
* @pdesc: Pointer to HW descriptor struct
|
|
* @size: Data unit size for XEX mode
|
|
*/
|
|
static inline void set_xex_data_unit_size(struct cc_hw_desc *pdesc, u32 size)
|
|
{
|
|
pdesc->word[2] = size;
|
|
}
|
|
|
|
/**
|
|
* set_multi2_num_rounds() - Set the number of rounds for Multi2 in
|
|
* data_out_addr[15:0]
|
|
*
|
|
* @pdesc: Pointer to HW descriptor struct
|
|
* @num: Number of rounds for Multi2
|
|
*/
|
|
static inline void set_multi2_num_rounds(struct cc_hw_desc *pdesc, u32 num)
|
|
{
|
|
pdesc->word[2] = num;
|
|
}
|
|
|
|
/**
|
|
* set_flow_mode() - Set the flow mode.
|
|
*
|
|
* @pdesc: Pointer to HW descriptor struct
|
|
* @mode: Any one of the modes defined in [CC7x-DESC]
|
|
*/
|
|
static inline void set_flow_mode(struct cc_hw_desc *pdesc,
|
|
enum cc_flow_mode mode)
|
|
{
|
|
pdesc->word[4] |= FIELD_PREP(WORD4_DATA_FLOW_MODE, mode);
|
|
}
|
|
|
|
/**
|
|
* set_cipher_mode() - Set the cipher mode.
|
|
*
|
|
* @pdesc: Pointer to HW descriptor struct
|
|
* @mode: Any one of the modes defined in [CC7x-DESC]
|
|
*/
|
|
static inline void set_cipher_mode(struct cc_hw_desc *pdesc, int mode)
|
|
{
|
|
pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_MODE, mode);
|
|
}
|
|
|
|
/**
|
|
* set_hash_cipher_mode() - Set the cipher mode for hash algorithms.
|
|
*
|
|
* @pdesc: Pointer to HW descriptor struct
|
|
* @cipher_mode: Any one of the modes defined in [CC7x-DESC]
|
|
* @hash_mode: specifies which hash is being handled
|
|
*/
|
|
static inline void set_hash_cipher_mode(struct cc_hw_desc *pdesc,
|
|
enum drv_cipher_mode cipher_mode,
|
|
enum drv_hash_mode hash_mode)
|
|
{
|
|
set_cipher_mode(pdesc, cipher_mode);
|
|
if (hash_mode == DRV_HASH_SM3)
|
|
set_aes_xor_crypto_key(pdesc);
|
|
}
|
|
|
|
/**
|
|
* set_cipher_config0() - Set the cipher configuration fields.
|
|
*
|
|
* @pdesc: Pointer to HW descriptor struct
|
|
* @mode: Any one of the modes defined in [CC7x-DESC]
|
|
*/
|
|
static inline void set_cipher_config0(struct cc_hw_desc *pdesc, int mode)
|
|
{
|
|
pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_CONF0, mode);
|
|
}
|
|
|
|
/**
|
|
* set_cipher_config1() - Set the cipher configuration fields.
|
|
*
|
|
* @pdesc: Pointer to HW descriptor struct
|
|
* @config: Padding mode
|
|
*/
|
|
static inline void set_cipher_config1(struct cc_hw_desc *pdesc,
|
|
enum cc_hash_conf_pad config)
|
|
{
|
|
pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_CONF1, config);
|
|
}
|
|
|
|
/**
|
|
* set_hw_crypto_key() - Set HW key configuration fields.
|
|
*
|
|
* @pdesc: Pointer to HW descriptor struct
|
|
* @hw_key: The HW key slot asdefined in enum cc_hw_crypto_key
|
|
*/
|
|
static inline void set_hw_crypto_key(struct cc_hw_desc *pdesc,
|
|
enum cc_hw_crypto_key hw_key)
|
|
{
|
|
pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_DO,
|
|
(hw_key & HW_KEY_MASK_CIPHER_DO)) |
|
|
FIELD_PREP(WORD4_CIPHER_CONF2,
|
|
(hw_key >> HW_KEY_SHIFT_CIPHER_CFG2));
|
|
}
|
|
|
|
/**
|
|
* set_bytes_swap() - Set byte order of all setup-finalize descriptors.
|
|
*
|
|
* @pdesc: Pointer to HW descriptor struct
|
|
* @config: True to enable byte swapping
|
|
*/
|
|
static inline void set_bytes_swap(struct cc_hw_desc *pdesc, bool config)
|
|
{
|
|
pdesc->word[4] |= FIELD_PREP(WORD4_BYTES_SWAP, config);
|
|
}
|
|
|
|
/**
|
|
* set_cmac_size0_mode() - Set CMAC_SIZE0 mode.
|
|
*
|
|
* @pdesc: Pointer to HW descriptor struct
|
|
*/
|
|
static inline void set_cmac_size0_mode(struct cc_hw_desc *pdesc)
|
|
{
|
|
pdesc->word[4] |= FIELD_PREP(WORD4_CMAC_SIZE0, 1);
|
|
}
|
|
|
|
/**
|
|
* set_key_size() - Set key size descriptor field.
|
|
*
|
|
* @pdesc: Pointer to HW descriptor struct
|
|
* @size: Key size in bytes (NOT size code)
|
|
*/
|
|
static inline void set_key_size(struct cc_hw_desc *pdesc, u32 size)
|
|
{
|
|
pdesc->word[4] |= FIELD_PREP(WORD4_KEY_SIZE, size);
|
|
}
|
|
|
|
/**
|
|
* set_key_size_aes() - Set AES key size.
|
|
*
|
|
* @pdesc: Pointer to HW descriptor struct
|
|
* @size: Key size in bytes (NOT size code)
|
|
*/
|
|
static inline void set_key_size_aes(struct cc_hw_desc *pdesc, u32 size)
|
|
{
|
|
set_key_size(pdesc, ((size >> 3) - 2));
|
|
}
|
|
|
|
/**
|
|
* set_key_size_des() - Set DES key size.
|
|
*
|
|
* @pdesc: Pointer to HW descriptor struct
|
|
* @size: Key size in bytes (NOT size code)
|
|
*/
|
|
static inline void set_key_size_des(struct cc_hw_desc *pdesc, u32 size)
|
|
{
|
|
set_key_size(pdesc, ((size >> 3) - 1));
|
|
}
|
|
|
|
/**
|
|
* set_setup_mode() - Set the descriptor setup mode
|
|
*
|
|
* @pdesc: Pointer to HW descriptor struct
|
|
* @mode: Any one of the setup modes defined in [CC7x-DESC]
|
|
*/
|
|
static inline void set_setup_mode(struct cc_hw_desc *pdesc,
|
|
enum cc_setup_op mode)
|
|
{
|
|
pdesc->word[4] |= FIELD_PREP(WORD4_SETUP_OPERATION, mode);
|
|
}
|
|
|
|
/**
|
|
* set_cipher_do() - Set the descriptor cipher DO
|
|
*
|
|
* @pdesc: Pointer to HW descriptor struct
|
|
* @config: Any one of the cipher do defined in [CC7x-DESC]
|
|
*/
|
|
static inline void set_cipher_do(struct cc_hw_desc *pdesc,
|
|
enum cc_hash_cipher_pad config)
|
|
{
|
|
pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_DO,
|
|
(config & HW_KEY_MASK_CIPHER_DO));
|
|
}
|
|
|
|
#endif /*__CC_HW_QUEUE_DEFS_H__*/
|