541 lines
13 KiB
C
541 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Ingenic XBurst SoCs SYSOST clocks driver
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* Copyright (c) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/interrupt.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/sched_clock.h>
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#include <linux/slab.h>
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#include <linux/syscore_ops.h>
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#include <dt-bindings/clock/ingenic,sysost.h>
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/* OST register offsets */
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#define OST_REG_OSTCCR 0x00
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#define OST_REG_OSTCR 0x08
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#define OST_REG_OSTFR 0x0c
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#define OST_REG_OSTMR 0x10
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#define OST_REG_OST1DFR 0x14
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#define OST_REG_OST1CNT 0x18
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#define OST_REG_OST2CNTL 0x20
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#define OST_REG_OSTCNT2HBUF 0x24
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#define OST_REG_OSTESR 0x34
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#define OST_REG_OSTECR 0x38
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/* bits within the OSTCCR register */
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#define OSTCCR_PRESCALE1_MASK 0x3
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#define OSTCCR_PRESCALE2_MASK 0xc
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/* bits within the OSTCR register */
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#define OSTCR_OST1CLR BIT(0)
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#define OSTCR_OST2CLR BIT(1)
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/* bits within the OSTFR register */
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#define OSTFR_FFLAG BIT(0)
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/* bits within the OSTMR register */
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#define OSTMR_FMASK BIT(0)
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/* bits within the OSTESR register */
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#define OSTESR_OST1ENS BIT(0)
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#define OSTESR_OST2ENS BIT(1)
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/* bits within the OSTECR register */
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#define OSTECR_OST1ENC BIT(0)
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#define OSTECR_OST2ENC BIT(1)
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struct ingenic_soc_info {
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unsigned int num_channels;
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};
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struct ingenic_ost_clk_info {
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struct clk_init_data init_data;
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u8 ostccr_reg;
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};
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struct ingenic_ost_clk {
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struct clk_hw hw;
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unsigned int idx;
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struct ingenic_ost *ost;
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const struct ingenic_ost_clk_info *info;
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};
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struct ingenic_ost {
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void __iomem *base;
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const struct ingenic_soc_info *soc_info;
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struct clk *clk, *percpu_timer_clk, *global_timer_clk;
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struct clock_event_device cevt;
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struct clocksource cs;
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char name[20];
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struct clk_hw_onecell_data *clocks;
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};
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static struct ingenic_ost *ingenic_ost;
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static inline struct ingenic_ost_clk *to_ost_clk(struct clk_hw *hw)
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{
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return container_of(hw, struct ingenic_ost_clk, hw);
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}
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static unsigned long ingenic_ost_percpu_timer_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct ingenic_ost_clk *ost_clk = to_ost_clk(hw);
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const struct ingenic_ost_clk_info *info = ost_clk->info;
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unsigned int prescale;
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prescale = readl(ost_clk->ost->base + info->ostccr_reg);
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prescale = FIELD_GET(OSTCCR_PRESCALE1_MASK, prescale);
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return parent_rate >> (prescale * 2);
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}
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static unsigned long ingenic_ost_global_timer_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct ingenic_ost_clk *ost_clk = to_ost_clk(hw);
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const struct ingenic_ost_clk_info *info = ost_clk->info;
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unsigned int prescale;
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prescale = readl(ost_clk->ost->base + info->ostccr_reg);
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prescale = FIELD_GET(OSTCCR_PRESCALE2_MASK, prescale);
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return parent_rate >> (prescale * 2);
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}
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static u8 ingenic_ost_get_prescale(unsigned long rate, unsigned long req_rate)
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{
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u8 prescale;
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for (prescale = 0; prescale < 2; prescale++)
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if ((rate >> (prescale * 2)) <= req_rate)
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return prescale;
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return 2; /* /16 divider */
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}
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static long ingenic_ost_round_rate(struct clk_hw *hw, unsigned long req_rate,
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unsigned long *parent_rate)
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{
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unsigned long rate = *parent_rate;
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u8 prescale;
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if (req_rate > rate)
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return rate;
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prescale = ingenic_ost_get_prescale(rate, req_rate);
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return rate >> (prescale * 2);
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}
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static int ingenic_ost_percpu_timer_set_rate(struct clk_hw *hw, unsigned long req_rate,
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unsigned long parent_rate)
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{
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struct ingenic_ost_clk *ost_clk = to_ost_clk(hw);
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const struct ingenic_ost_clk_info *info = ost_clk->info;
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u8 prescale = ingenic_ost_get_prescale(parent_rate, req_rate);
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int val;
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val = readl(ost_clk->ost->base + info->ostccr_reg);
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val &= ~OSTCCR_PRESCALE1_MASK;
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val |= FIELD_PREP(OSTCCR_PRESCALE1_MASK, prescale);
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writel(val, ost_clk->ost->base + info->ostccr_reg);
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return 0;
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}
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static int ingenic_ost_global_timer_set_rate(struct clk_hw *hw, unsigned long req_rate,
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unsigned long parent_rate)
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{
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struct ingenic_ost_clk *ost_clk = to_ost_clk(hw);
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const struct ingenic_ost_clk_info *info = ost_clk->info;
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u8 prescale = ingenic_ost_get_prescale(parent_rate, req_rate);
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int val;
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val = readl(ost_clk->ost->base + info->ostccr_reg);
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val &= ~OSTCCR_PRESCALE2_MASK;
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val |= FIELD_PREP(OSTCCR_PRESCALE2_MASK, prescale);
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writel(val, ost_clk->ost->base + info->ostccr_reg);
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return 0;
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}
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static const struct clk_ops ingenic_ost_percpu_timer_ops = {
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.recalc_rate = ingenic_ost_percpu_timer_recalc_rate,
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.round_rate = ingenic_ost_round_rate,
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.set_rate = ingenic_ost_percpu_timer_set_rate,
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};
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static const struct clk_ops ingenic_ost_global_timer_ops = {
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.recalc_rate = ingenic_ost_global_timer_recalc_rate,
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.round_rate = ingenic_ost_round_rate,
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.set_rate = ingenic_ost_global_timer_set_rate,
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};
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static const char * const ingenic_ost_clk_parents[] = { "ext" };
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static const struct ingenic_ost_clk_info x1000_ost_clk_info[] = {
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[OST_CLK_PERCPU_TIMER] = {
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.init_data = {
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.name = "percpu timer",
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.parent_names = ingenic_ost_clk_parents,
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.num_parents = ARRAY_SIZE(ingenic_ost_clk_parents),
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.ops = &ingenic_ost_percpu_timer_ops,
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.flags = CLK_SET_RATE_UNGATE,
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},
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.ostccr_reg = OST_REG_OSTCCR,
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},
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[OST_CLK_GLOBAL_TIMER] = {
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.init_data = {
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.name = "global timer",
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.parent_names = ingenic_ost_clk_parents,
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.num_parents = ARRAY_SIZE(ingenic_ost_clk_parents),
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.ops = &ingenic_ost_global_timer_ops,
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.flags = CLK_SET_RATE_UNGATE,
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},
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.ostccr_reg = OST_REG_OSTCCR,
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},
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};
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static u64 notrace ingenic_ost_global_timer_read_cntl(void)
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{
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struct ingenic_ost *ost = ingenic_ost;
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unsigned int count;
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count = readl(ost->base + OST_REG_OST2CNTL);
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return count;
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}
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static u64 notrace ingenic_ost_clocksource_read(struct clocksource *cs)
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{
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return ingenic_ost_global_timer_read_cntl();
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}
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static inline struct ingenic_ost *to_ingenic_ost(struct clock_event_device *evt)
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{
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return container_of(evt, struct ingenic_ost, cevt);
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}
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static int ingenic_ost_cevt_set_state_shutdown(struct clock_event_device *evt)
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{
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struct ingenic_ost *ost = to_ingenic_ost(evt);
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writel(OSTECR_OST1ENC, ost->base + OST_REG_OSTECR);
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return 0;
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}
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static int ingenic_ost_cevt_set_next(unsigned long next,
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struct clock_event_device *evt)
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{
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struct ingenic_ost *ost = to_ingenic_ost(evt);
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writel((u32)~OSTFR_FFLAG, ost->base + OST_REG_OSTFR);
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writel(next, ost->base + OST_REG_OST1DFR);
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writel(OSTCR_OST1CLR, ost->base + OST_REG_OSTCR);
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writel(OSTESR_OST1ENS, ost->base + OST_REG_OSTESR);
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writel((u32)~OSTMR_FMASK, ost->base + OST_REG_OSTMR);
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return 0;
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}
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static irqreturn_t ingenic_ost_cevt_cb(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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struct ingenic_ost *ost = to_ingenic_ost(evt);
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writel(OSTECR_OST1ENC, ost->base + OST_REG_OSTECR);
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if (evt->event_handler)
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static int __init ingenic_ost_register_clock(struct ingenic_ost *ost,
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unsigned int idx, const struct ingenic_ost_clk_info *info,
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struct clk_hw_onecell_data *clocks)
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{
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struct ingenic_ost_clk *ost_clk;
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int val, err;
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ost_clk = kzalloc(sizeof(*ost_clk), GFP_KERNEL);
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if (!ost_clk)
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return -ENOMEM;
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ost_clk->hw.init = &info->init_data;
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ost_clk->idx = idx;
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ost_clk->info = info;
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ost_clk->ost = ost;
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/* Reset clock divider */
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val = readl(ost->base + info->ostccr_reg);
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val &= ~(OSTCCR_PRESCALE1_MASK | OSTCCR_PRESCALE2_MASK);
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writel(val, ost->base + info->ostccr_reg);
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err = clk_hw_register(NULL, &ost_clk->hw);
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if (err) {
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kfree(ost_clk);
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return err;
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}
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clocks->hws[idx] = &ost_clk->hw;
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return 0;
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}
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static struct clk * __init ingenic_ost_get_clock(struct device_node *np, int id)
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{
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struct of_phandle_args args;
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args.np = np;
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args.args_count = 1;
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args.args[0] = id;
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return of_clk_get_from_provider(&args);
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}
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static int __init ingenic_ost_percpu_timer_init(struct device_node *np,
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struct ingenic_ost *ost)
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{
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unsigned int timer_virq, channel = OST_CLK_PERCPU_TIMER;
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unsigned long rate;
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int err;
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ost->percpu_timer_clk = ingenic_ost_get_clock(np, channel);
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if (IS_ERR(ost->percpu_timer_clk))
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return PTR_ERR(ost->percpu_timer_clk);
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err = clk_prepare_enable(ost->percpu_timer_clk);
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if (err)
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goto err_clk_put;
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rate = clk_get_rate(ost->percpu_timer_clk);
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if (!rate) {
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err = -EINVAL;
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goto err_clk_disable;
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}
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timer_virq = of_irq_get(np, 0);
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if (!timer_virq) {
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err = -EINVAL;
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goto err_clk_disable;
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}
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snprintf(ost->name, sizeof(ost->name), "OST percpu timer");
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err = request_irq(timer_virq, ingenic_ost_cevt_cb, IRQF_TIMER,
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ost->name, &ost->cevt);
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if (err)
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goto err_irq_dispose_mapping;
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ost->cevt.cpumask = cpumask_of(smp_processor_id());
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ost->cevt.features = CLOCK_EVT_FEAT_ONESHOT;
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ost->cevt.name = ost->name;
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ost->cevt.rating = 400;
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ost->cevt.set_state_shutdown = ingenic_ost_cevt_set_state_shutdown;
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ost->cevt.set_next_event = ingenic_ost_cevt_set_next;
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clockevents_config_and_register(&ost->cevt, rate, 4, 0xffffffff);
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return 0;
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err_irq_dispose_mapping:
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irq_dispose_mapping(timer_virq);
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err_clk_disable:
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clk_disable_unprepare(ost->percpu_timer_clk);
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err_clk_put:
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clk_put(ost->percpu_timer_clk);
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return err;
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}
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static int __init ingenic_ost_global_timer_init(struct device_node *np,
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struct ingenic_ost *ost)
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{
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unsigned int channel = OST_CLK_GLOBAL_TIMER;
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struct clocksource *cs = &ost->cs;
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unsigned long rate;
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int err;
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ost->global_timer_clk = ingenic_ost_get_clock(np, channel);
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if (IS_ERR(ost->global_timer_clk))
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return PTR_ERR(ost->global_timer_clk);
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err = clk_prepare_enable(ost->global_timer_clk);
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if (err)
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goto err_clk_put;
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rate = clk_get_rate(ost->global_timer_clk);
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if (!rate) {
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err = -EINVAL;
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goto err_clk_disable;
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}
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/* Clear counter CNT registers */
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writel(OSTCR_OST2CLR, ost->base + OST_REG_OSTCR);
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/* Enable OST channel */
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writel(OSTESR_OST2ENS, ost->base + OST_REG_OSTESR);
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cs->name = "ingenic-ost";
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cs->rating = 400;
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cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
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cs->mask = CLOCKSOURCE_MASK(32);
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cs->read = ingenic_ost_clocksource_read;
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err = clocksource_register_hz(cs, rate);
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if (err)
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goto err_clk_disable;
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return 0;
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err_clk_disable:
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clk_disable_unprepare(ost->global_timer_clk);
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err_clk_put:
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clk_put(ost->global_timer_clk);
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return err;
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}
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static const struct ingenic_soc_info x1000_soc_info = {
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.num_channels = 2,
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};
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static const struct of_device_id __maybe_unused ingenic_ost_of_matches[] __initconst = {
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{ .compatible = "ingenic,x1000-ost", .data = &x1000_soc_info },
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{ /* sentinel */ }
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};
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static int __init ingenic_ost_probe(struct device_node *np)
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{
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const struct of_device_id *id = of_match_node(ingenic_ost_of_matches, np);
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struct ingenic_ost *ost;
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unsigned int i;
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int ret;
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ost = kzalloc(sizeof(*ost), GFP_KERNEL);
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if (!ost)
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return -ENOMEM;
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ost->base = of_io_request_and_map(np, 0, of_node_full_name(np));
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if (IS_ERR(ost->base)) {
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pr_err("%s: Failed to map OST registers\n", __func__);
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ret = PTR_ERR(ost->base);
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goto err_free_ost;
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}
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ost->clk = of_clk_get_by_name(np, "ost");
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if (IS_ERR(ost->clk)) {
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ret = PTR_ERR(ost->clk);
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pr_crit("%s: Cannot get OST clock\n", __func__);
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goto err_free_ost;
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}
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ret = clk_prepare_enable(ost->clk);
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if (ret) {
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pr_crit("%s: Unable to enable OST clock\n", __func__);
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goto err_put_clk;
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}
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ost->soc_info = id->data;
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ost->clocks = kzalloc(struct_size(ost->clocks, hws, ost->soc_info->num_channels),
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GFP_KERNEL);
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if (!ost->clocks) {
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ret = -ENOMEM;
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goto err_clk_disable;
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}
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ost->clocks->num = ost->soc_info->num_channels;
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for (i = 0; i < ost->clocks->num; i++) {
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ret = ingenic_ost_register_clock(ost, i, &x1000_ost_clk_info[i], ost->clocks);
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if (ret) {
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pr_crit("%s: Cannot register clock %d\n", __func__, i);
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goto err_unregister_ost_clocks;
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}
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}
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ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, ost->clocks);
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if (ret) {
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pr_crit("%s: Cannot add OF clock provider\n", __func__);
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goto err_unregister_ost_clocks;
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}
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ingenic_ost = ost;
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return 0;
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err_unregister_ost_clocks:
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for (i = 0; i < ost->clocks->num; i++)
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if (ost->clocks->hws[i])
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clk_hw_unregister(ost->clocks->hws[i]);
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kfree(ost->clocks);
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err_clk_disable:
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clk_disable_unprepare(ost->clk);
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err_put_clk:
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clk_put(ost->clk);
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err_free_ost:
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kfree(ost);
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return ret;
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}
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static int __init ingenic_ost_init(struct device_node *np)
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{
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struct ingenic_ost *ost;
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unsigned long rate;
|
|
int ret;
|
|
|
|
ret = ingenic_ost_probe(np);
|
|
if (ret) {
|
|
pr_crit("%s: Failed to initialize OST clocks: %d\n", __func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
of_node_clear_flag(np, OF_POPULATED);
|
|
|
|
ost = ingenic_ost;
|
|
if (IS_ERR(ost))
|
|
return PTR_ERR(ost);
|
|
|
|
ret = ingenic_ost_global_timer_init(np, ost);
|
|
if (ret) {
|
|
pr_crit("%s: Unable to init global timer: %x\n", __func__, ret);
|
|
goto err_free_ingenic_ost;
|
|
}
|
|
|
|
ret = ingenic_ost_percpu_timer_init(np, ost);
|
|
if (ret)
|
|
goto err_ost_global_timer_cleanup;
|
|
|
|
/* Register the sched_clock at the end as there's no way to undo it */
|
|
rate = clk_get_rate(ost->global_timer_clk);
|
|
sched_clock_register(ingenic_ost_global_timer_read_cntl, 32, rate);
|
|
|
|
return 0;
|
|
|
|
err_ost_global_timer_cleanup:
|
|
clocksource_unregister(&ost->cs);
|
|
clk_disable_unprepare(ost->global_timer_clk);
|
|
clk_put(ost->global_timer_clk);
|
|
err_free_ingenic_ost:
|
|
kfree(ost);
|
|
return ret;
|
|
}
|
|
|
|
TIMER_OF_DECLARE(x1000_ost, "ingenic,x1000-ost", ingenic_ost_init);
|