70 lines
1.3 KiB
C
70 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright 2016 Chen-Yu Tsai
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*
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* Chen-Yu Tsai <wens@csie.org>
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*/
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#ifndef _CCU_SUN6I_A31_H_
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#define _CCU_SUN6I_A31_H_
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#include <dt-bindings/clock/sun6i-a31-ccu.h>
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#include <dt-bindings/reset/sun6i-a31-ccu.h>
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#define CLK_PLL_CPU 0
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#define CLK_PLL_AUDIO_BASE 1
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#define CLK_PLL_AUDIO 2
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#define CLK_PLL_AUDIO_2X 3
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#define CLK_PLL_AUDIO_4X 4
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#define CLK_PLL_AUDIO_8X 5
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#define CLK_PLL_VIDEO0 6
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/* The PLL_VIDEO0_2X clock is exported */
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#define CLK_PLL_VE 8
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#define CLK_PLL_DDR 9
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/* The PLL_PERIPH clock is exported */
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#define CLK_PLL_PERIPH_2X 11
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#define CLK_PLL_VIDEO1 12
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/* The PLL_VIDEO1_2X clock is exported */
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#define CLK_PLL_GPU 14
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/* The PLL_VIDEO1_2X clock is exported */
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#define CLK_PLL9 16
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#define CLK_PLL10 17
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/* The CPUX clock is exported */
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#define CLK_AXI 19
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#define CLK_AHB1 20
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#define CLK_APB1 21
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#define CLK_APB2 22
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/* All the bus gates are exported */
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/* The first bunch of module clocks are exported */
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/* EMAC clock is not implemented */
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#define CLK_MDFS 107
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#define CLK_SDRAM0 108
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#define CLK_SDRAM1 109
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/* All the DRAM gates are exported */
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/* Some more module clocks are exported */
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#define CLK_MBUS0 141
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#define CLK_MBUS1 142
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/* Some more module clocks and external clock outputs are exported */
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#define CLK_NUMBER (CLK_OUT_C + 1)
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#endif /* _CCU_SUN6I_A31_H_ */
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