227 lines
5.9 KiB
C
227 lines
5.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* R7S9210 Clock Pulse Generator / Module Standby
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*
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* Based on r8a7795-cpg-mssr.c
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*
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* Copyright (C) 2018 Chris Brandt
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* Copyright (C) 2018 Renesas Electronics Corp.
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*
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <dt-bindings/clock/r7s9210-cpg-mssr.h>
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#include "renesas-cpg-mssr.h"
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#define CPG_FRQCR 0x00
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static u8 cpg_mode;
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/* Internal Clock ratio table */
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static const struct {
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unsigned int i;
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unsigned int g;
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unsigned int b;
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unsigned int p1;
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/* p0 is always 32 */;
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} ratio_tab[5] = { /* I, G, B, P1 */
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{ 2, 4, 8, 16}, /* FRQCR = 0x012 */
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{ 4, 4, 8, 16}, /* FRQCR = 0x112 */
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{ 8, 4, 8, 16}, /* FRQCR = 0x212 */
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{ 16, 8, 16, 16}, /* FRQCR = 0x322 */
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{ 16, 16, 32, 32}, /* FRQCR = 0x333 */
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};
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enum rz_clk_types {
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CLK_TYPE_RZA_MAIN = CLK_TYPE_CUSTOM,
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CLK_TYPE_RZA_PLL,
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};
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R7S9210_CLK_P0,
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/* External Input Clocks */
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CLK_EXTAL,
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/* Internal Core Clocks */
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CLK_MAIN,
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CLK_PLL,
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/* Module Clocks */
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MOD_CLK_BASE
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};
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static struct cpg_core_clk r7s9210_early_core_clks[] = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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/* Internal Core Clocks */
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DEF_BASE(".main", CLK_MAIN, CLK_TYPE_RZA_MAIN, CLK_EXTAL),
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DEF_BASE(".pll", CLK_PLL, CLK_TYPE_RZA_PLL, CLK_MAIN),
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/* Core Clock Outputs */
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DEF_FIXED("p1c", R7S9210_CLK_P1C, CLK_PLL, 16, 1),
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};
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static const struct mssr_mod_clk r7s9210_early_mod_clks[] __initconst = {
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DEF_MOD_STB("ostm2", 34, R7S9210_CLK_P1C),
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DEF_MOD_STB("ostm1", 35, R7S9210_CLK_P1C),
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DEF_MOD_STB("ostm0", 36, R7S9210_CLK_P1C),
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};
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static struct cpg_core_clk r7s9210_core_clks[] = {
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/* Core Clock Outputs */
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DEF_FIXED("i", R7S9210_CLK_I, CLK_PLL, 2, 1),
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DEF_FIXED("g", R7S9210_CLK_G, CLK_PLL, 4, 1),
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DEF_FIXED("b", R7S9210_CLK_B, CLK_PLL, 8, 1),
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DEF_FIXED("p1", R7S9210_CLK_P1, CLK_PLL, 16, 1),
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DEF_FIXED("p0", R7S9210_CLK_P0, CLK_PLL, 32, 1),
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};
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static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = {
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DEF_MOD_STB("scif4", 43, R7S9210_CLK_P1C),
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DEF_MOD_STB("scif3", 44, R7S9210_CLK_P1C),
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DEF_MOD_STB("scif2", 45, R7S9210_CLK_P1C),
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DEF_MOD_STB("scif1", 46, R7S9210_CLK_P1C),
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DEF_MOD_STB("scif0", 47, R7S9210_CLK_P1C),
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DEF_MOD_STB("usb1", 60, R7S9210_CLK_B),
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DEF_MOD_STB("usb0", 61, R7S9210_CLK_B),
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DEF_MOD_STB("ether1", 64, R7S9210_CLK_B),
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DEF_MOD_STB("ether0", 65, R7S9210_CLK_B),
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DEF_MOD_STB("spibsc", 83, R7S9210_CLK_P1),
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DEF_MOD_STB("i2c3", 84, R7S9210_CLK_P1),
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DEF_MOD_STB("i2c2", 85, R7S9210_CLK_P1),
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DEF_MOD_STB("i2c1", 86, R7S9210_CLK_P1),
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DEF_MOD_STB("i2c0", 87, R7S9210_CLK_P1),
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DEF_MOD_STB("spi2", 95, R7S9210_CLK_P1),
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DEF_MOD_STB("spi1", 96, R7S9210_CLK_P1),
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DEF_MOD_STB("spi0", 97, R7S9210_CLK_P1),
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DEF_MOD_STB("sdhi11", 100, R7S9210_CLK_B),
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DEF_MOD_STB("sdhi10", 101, R7S9210_CLK_B),
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DEF_MOD_STB("sdhi01", 102, R7S9210_CLK_B),
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DEF_MOD_STB("sdhi00", 103, R7S9210_CLK_B),
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};
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/* The clock dividers in the table vary based on DT and register settings */
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static void __init r7s9210_update_clk_table(struct clk *extal_clk,
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void __iomem *base)
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{
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int i;
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u16 frqcr;
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u8 index;
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/* If EXTAL is above 12MHz, then we know it is Mode 1 */
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if (clk_get_rate(extal_clk) > 12000000)
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cpg_mode = 1;
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frqcr = readl(base + CPG_FRQCR) & 0xFFF;
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if (frqcr == 0x012)
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index = 0;
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else if (frqcr == 0x112)
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index = 1;
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else if (frqcr == 0x212)
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index = 2;
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else if (frqcr == 0x322)
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index = 3;
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else if (frqcr == 0x333)
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index = 4;
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else
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BUG_ON(1); /* Illegal FRQCR value */
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for (i = 0; i < ARRAY_SIZE(r7s9210_core_clks); i++) {
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switch (r7s9210_core_clks[i].id) {
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case R7S9210_CLK_I:
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r7s9210_core_clks[i].div = ratio_tab[index].i;
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break;
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case R7S9210_CLK_G:
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r7s9210_core_clks[i].div = ratio_tab[index].g;
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break;
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case R7S9210_CLK_B:
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r7s9210_core_clks[i].div = ratio_tab[index].b;
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break;
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case R7S9210_CLK_P1:
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case R7S9210_CLK_P1C:
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r7s9210_core_clks[i].div = ratio_tab[index].p1;
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break;
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case R7S9210_CLK_P0:
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r7s9210_core_clks[i].div = 32;
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break;
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}
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}
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}
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static struct clk * __init rza2_cpg_clk_register(struct device *dev,
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const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
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struct clk **clks, void __iomem *base,
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struct raw_notifier_head *notifiers)
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{
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struct clk *parent;
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unsigned int mult = 1;
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unsigned int div = 1;
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parent = clks[core->parent];
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if (IS_ERR(parent))
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return ERR_CAST(parent);
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switch (core->id) {
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case CLK_MAIN:
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break;
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case CLK_PLL:
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if (cpg_mode)
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mult = 44; /* Divider 1 is 1/2 */
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else
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mult = 88; /* Divider 1 is 1 */
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break;
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default:
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return ERR_PTR(-EINVAL);
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}
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if (core->id == CLK_MAIN)
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r7s9210_update_clk_table(parent, base);
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return clk_register_fixed_factor(NULL, core->name,
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__clk_get_name(parent), 0, mult, div);
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}
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const struct cpg_mssr_info r7s9210_cpg_mssr_info __initconst = {
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/* Early Clocks */
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.early_core_clks = r7s9210_early_core_clks,
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.num_early_core_clks = ARRAY_SIZE(r7s9210_early_core_clks),
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.early_mod_clks = r7s9210_early_mod_clks,
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.num_early_mod_clks = ARRAY_SIZE(r7s9210_early_mod_clks),
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/* Core Clocks */
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.core_clks = r7s9210_core_clks,
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.num_core_clks = ARRAY_SIZE(r7s9210_core_clks),
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.last_dt_core_clk = LAST_DT_CORE_CLK,
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.num_total_core_clks = MOD_CLK_BASE,
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/* Module Clocks */
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.mod_clks = r7s9210_mod_clks,
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.num_mod_clks = ARRAY_SIZE(r7s9210_mod_clks),
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.num_hw_mod_clks = 11 * 32, /* includes STBCR0 which doesn't exist */
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/* Callbacks */
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.cpg_clk_register = rza2_cpg_clk_register,
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/* RZ/A2 has Standby Control Registers */
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.reg_layout = CLK_REG_LAYOUT_RZ_A,
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};
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static void __init r7s9210_cpg_mssr_early_init(struct device_node *np)
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{
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cpg_mssr_early_init(np, &r7s9210_cpg_mssr_info);
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}
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CLK_OF_DECLARE_DRIVER(cpg_mstp_clks, "renesas,r7s9210-cpg-mssr",
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r7s9210_cpg_mssr_early_init);
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