556 lines
14 KiB
C
556 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2021, Linaro Ltd.
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*/
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "clk-regmap-divider.h"
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#include "common.h"
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#include "gdsc.h"
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enum {
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P_BI_TCXO,
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P_DISP_CC_PLL0_OUT_MAIN,
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P_DSI0_PHY_PLL_OUT_BYTECLK,
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P_DSI0_PHY_PLL_OUT_DSICLK,
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P_DSI1_PHY_PLL_OUT_DSICLK,
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P_GPLL0_OUT_MAIN,
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P_SLEEP_CLK,
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};
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static const struct pll_vco spark_vco[] = {
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{ 500000000, 1000000000, 2 },
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};
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/* 768MHz configuration */
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static const struct alpha_pll_config disp_cc_pll0_config = {
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.l = 0x28,
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.alpha = 0x0,
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.alpha_en_mask = BIT(24),
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.vco_val = 0x2 << 20,
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.vco_mask = GENMASK(21, 20),
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.main_output_mask = BIT(0),
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.config_ctl_val = 0x4001055B,
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};
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static struct clk_alpha_pll disp_cc_pll0 = {
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.offset = 0x0,
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.vco_table = spark_vco,
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.num_vco = ARRAY_SIZE(spark_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_pll0",
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "bi_tcxo",
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_ops,
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},
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},
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};
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static const struct parent_map disp_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
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};
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static const struct clk_parent_data disp_cc_parent_data_0[] = {
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{ .fw_name = "bi_tcxo" },
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{ .fw_name = "dsi0_phy_pll_out_byteclk" },
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{ .fw_name = "core_bi_pll_test_se" },
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};
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static const struct parent_map disp_cc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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};
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static const struct clk_parent_data disp_cc_parent_data_1[] = {
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{ .fw_name = "bi_tcxo" },
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{ .fw_name = "core_bi_pll_test_se" },
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};
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static const struct parent_map disp_cc_parent_map_2[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPLL0_OUT_MAIN, 4 },
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};
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static const struct clk_parent_data disp_cc_parent_data_2[] = {
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{ .fw_name = "bi_tcxo_ao" },
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{ .fw_name = "gcc_disp_gpll0_div_clk_src" },
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{ .fw_name = "core_bi_pll_test_se" },
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};
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static const struct parent_map disp_cc_parent_map_3[] = {
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{ P_BI_TCXO, 0 },
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{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
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{ P_GPLL0_OUT_MAIN, 4 },
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};
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static const struct clk_parent_data disp_cc_parent_data_3[] = {
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{ .fw_name = "bi_tcxo" },
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{ .hw = &disp_cc_pll0.clkr.hw },
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{ .fw_name = "gcc_disp_gpll0_clk_src" },
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{ .fw_name = "core_bi_pll_test_se" },
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};
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static const struct parent_map disp_cc_parent_map_4[] = {
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{ P_BI_TCXO, 0 },
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{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
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{ P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
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};
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static const struct clk_parent_data disp_cc_parent_data_4[] = {
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{ .fw_name = "bi_tcxo" },
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{ .fw_name = "dsi0_phy_pll_out_dsiclk" },
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{ .fw_name = "dsi1_phy_pll_out_dsiclk" },
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{ .fw_name = "core_bi_pll_test_se" },
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};
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static const struct parent_map disp_cc_parent_map_5[] = {
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{ P_SLEEP_CLK, 0 },
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};
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static const struct clk_parent_data disp_cc_parent_data_5[] = {
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{ .fw_name = "sleep_clk" },
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{ .fw_name = "core_bi_pll_test_se" },
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};
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static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
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.cmd_rcgr = 0x20a4,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_0,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_byte0_clk_src",
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.parent_data = disp_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
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/* For set_rate and set_parent to succeed, parent(s) must be enabled */
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.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
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.ops = &clk_byte2_ops,
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},
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};
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static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
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.reg = 0x20bc,
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.shift = 0,
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.width = 2,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "disp_cc_mdss_byte0_div_clk_src",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_byte0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.ops = &clk_regmap_div_ops,
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},
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};
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static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(37500000, P_GPLL0_OUT_MAIN, 8, 0, 0),
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F(75000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
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{ }
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};
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static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
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.cmd_rcgr = 0x2154,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_2,
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.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_ahb_clk_src",
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.parent_data = disp_cc_parent_data_2,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
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.cmd_rcgr = 0x20c0,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_0,
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.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_esc0_clk_src",
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.parent_data = disp_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
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.ops = &clk_rcg2_ops,
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},
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};
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static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
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F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
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F(307200000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
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F(384000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
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{ }
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};
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static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
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.cmd_rcgr = 0x2074,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_3,
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.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_mdp_clk_src",
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.parent_data = disp_cc_parent_data_3,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
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.cmd_rcgr = 0x205c,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_4,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_pclk0_clk_src",
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.parent_data = disp_cc_parent_data_4,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
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/* For set_rate and set_parent to succeed, parent(s) must be enabled */
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.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
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.ops = &clk_pixel_ops,
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},
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};
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static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
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.cmd_rcgr = 0x208c,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_1,
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.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_vsync_clk_src",
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.parent_data = disp_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = {
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F(32764, P_SLEEP_CLK, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 disp_cc_sleep_clk_src = {
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.cmd_rcgr = 0x6050,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_parent_map_5,
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.freq_tbl = ftbl_disp_cc_sleep_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_sleep_clk_src",
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.parent_data = disp_cc_parent_data_5,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
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.ops = &clk_rcg2_ops,
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},
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};
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static struct clk_branch disp_cc_mdss_ahb_clk = {
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.halt_reg = 0x2044,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x2044,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_ahb_clk",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_ahb_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch disp_cc_mdss_byte0_clk = {
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.halt_reg = 0x201c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x201c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_byte0_clk",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_byte0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
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.halt_reg = 0x2020,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x2020,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_byte0_intf_clk",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch disp_cc_mdss_esc0_clk = {
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.halt_reg = 0x2024,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x2024,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_esc0_clk",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_esc0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch disp_cc_mdss_mdp_clk = {
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.halt_reg = 0x2008,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x2008,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_mdp_clk",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_mdp_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
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.halt_reg = 0x2010,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x2010,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_mdp_lut_clk",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_mdp_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
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.halt_reg = 0x4004,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x4004,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_non_gdsc_ahb_clk",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_ahb_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch disp_cc_mdss_pclk0_clk = {
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.halt_reg = 0x2004,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x2004,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_pclk0_clk",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_pclk0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch disp_cc_mdss_vsync_clk = {
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.halt_reg = 0x2018,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x2018,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_vsync_clk",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_vsync_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch disp_cc_sleep_clk = {
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.halt_reg = 0x6068,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x6068,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_sleep_clk",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_sleep_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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|
|
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static struct gdsc mdss_gdsc = {
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.gdscr = 0x3000,
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.pd = {
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.name = "mdss_gdsc",
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},
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.pwrsts = PWRSTS_OFF_ON,
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.flags = HW_CTRL,
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|
};
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|
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static struct gdsc *disp_cc_qcm2290_gdscs[] = {
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[MDSS_GDSC] = &mdss_gdsc,
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|
};
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|
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static struct clk_regmap *disp_cc_qcm2290_clocks[] = {
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[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
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[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
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[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
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[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
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[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
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[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
|
|
[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
|
|
[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
|
|
[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
|
|
[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
|
|
[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
|
|
[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
|
|
[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
|
|
[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
|
|
[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
|
|
[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
|
|
[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
|
|
[DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr,
|
|
[DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr,
|
|
};
|
|
|
|
static const struct regmap_config disp_cc_qcm2290_regmap_config = {
|
|
.reg_bits = 32,
|
|
.reg_stride = 4,
|
|
.val_bits = 32,
|
|
.max_register = 0x10000,
|
|
.fast_io = true,
|
|
};
|
|
|
|
static const struct qcom_cc_desc disp_cc_qcm2290_desc = {
|
|
.config = &disp_cc_qcm2290_regmap_config,
|
|
.clks = disp_cc_qcm2290_clocks,
|
|
.num_clks = ARRAY_SIZE(disp_cc_qcm2290_clocks),
|
|
.gdscs = disp_cc_qcm2290_gdscs,
|
|
.num_gdscs = ARRAY_SIZE(disp_cc_qcm2290_gdscs),
|
|
};
|
|
|
|
static const struct of_device_id disp_cc_qcm2290_match_table[] = {
|
|
{ .compatible = "qcom,qcm2290-dispcc" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, disp_cc_qcm2290_match_table);
|
|
|
|
static int disp_cc_qcm2290_probe(struct platform_device *pdev)
|
|
{
|
|
struct regmap *regmap;
|
|
int ret;
|
|
|
|
regmap = qcom_cc_map(pdev, &disp_cc_qcm2290_desc);
|
|
if (IS_ERR(regmap))
|
|
return PTR_ERR(regmap);
|
|
|
|
clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
|
|
|
|
/* Keep DISP_CC_XO_CLK always-ON */
|
|
regmap_update_bits(regmap, 0x604c, BIT(0), BIT(0));
|
|
|
|
ret = qcom_cc_really_probe(pdev, &disp_cc_qcm2290_desc, regmap);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to register DISP CC clocks\n");
|
|
return ret;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct platform_driver disp_cc_qcm2290_driver = {
|
|
.probe = disp_cc_qcm2290_probe,
|
|
.driver = {
|
|
.name = "dispcc-qcm2290",
|
|
.of_match_table = disp_cc_qcm2290_match_table,
|
|
},
|
|
};
|
|
|
|
static int __init disp_cc_qcm2290_init(void)
|
|
{
|
|
return platform_driver_register(&disp_cc_qcm2290_driver);
|
|
}
|
|
subsys_initcall(disp_cc_qcm2290_init);
|
|
|
|
static void __exit disp_cc_qcm2290_exit(void)
|
|
{
|
|
platform_driver_unregister(&disp_cc_qcm2290_driver);
|
|
}
|
|
module_exit(disp_cc_qcm2290_exit);
|
|
|
|
MODULE_DESCRIPTION("QTI DISP_CC qcm2290 Driver");
|
|
MODULE_LICENSE("GPL v2");
|