302 lines
7.2 KiB
C
302 lines
7.2 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
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/*
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* Copyright (c) 2016 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include <linux/platform_device.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include "meson-aoclk.h"
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#include "gxbb-aoclk.h"
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#include "clk-regmap.h"
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#include "clk-dualdiv.h"
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/* AO Configuration Clock registers offsets */
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#define AO_RTI_PWR_CNTL_REG1 0x0c
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#define AO_RTI_PWR_CNTL_REG0 0x10
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#define AO_RTI_GEN_CNTL_REG0 0x40
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#define AO_OSCIN_CNTL 0x58
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#define AO_CRT_CLK_CNTL1 0x68
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#define AO_RTC_ALT_CLK_CNTL0 0x94
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#define AO_RTC_ALT_CLK_CNTL1 0x98
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#define GXBB_AO_GATE(_name, _bit) \
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static struct clk_regmap _name##_ao = { \
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.data = &(struct clk_regmap_gate_data) { \
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.offset = AO_RTI_GEN_CNTL_REG0, \
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.bit_idx = (_bit), \
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}, \
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.hw.init = &(struct clk_init_data) { \
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.name = #_name "_ao", \
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.ops = &clk_regmap_gate_ops, \
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.parent_data = &(const struct clk_parent_data) { \
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.fw_name = "mpeg-clk", \
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}, \
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.num_parents = 1, \
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.flags = CLK_IGNORE_UNUSED, \
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}, \
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}
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GXBB_AO_GATE(remote, 0);
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GXBB_AO_GATE(i2c_master, 1);
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GXBB_AO_GATE(i2c_slave, 2);
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GXBB_AO_GATE(uart1, 3);
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GXBB_AO_GATE(uart2, 5);
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GXBB_AO_GATE(ir_blaster, 6);
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static struct clk_regmap ao_cts_oscin = {
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.data = &(struct clk_regmap_gate_data){
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.offset = AO_RTI_PWR_CNTL_REG0,
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.bit_idx = 6,
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},
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.hw.init = &(struct clk_init_data){
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.name = "ao_cts_oscin",
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.ops = &clk_regmap_gate_ro_ops,
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "xtal",
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},
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.num_parents = 1,
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},
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};
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static struct clk_regmap ao_32k_pre = {
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.data = &(struct clk_regmap_gate_data){
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.offset = AO_RTC_ALT_CLK_CNTL0,
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.bit_idx = 31,
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},
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.hw.init = &(struct clk_init_data){
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.name = "ao_32k_pre",
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.ops = &clk_regmap_gate_ops,
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.parent_hws = (const struct clk_hw *[]) { &ao_cts_oscin.hw },
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.num_parents = 1,
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},
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};
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static const struct meson_clk_dualdiv_param gxbb_32k_div_table[] = {
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{
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.dual = 1,
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.n1 = 733,
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.m1 = 8,
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.n2 = 732,
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.m2 = 11,
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}, {}
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};
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static struct clk_regmap ao_32k_div = {
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.data = &(struct meson_clk_dualdiv_data){
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.n1 = {
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.reg_off = AO_RTC_ALT_CLK_CNTL0,
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.shift = 0,
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.width = 12,
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},
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.n2 = {
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.reg_off = AO_RTC_ALT_CLK_CNTL0,
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.shift = 12,
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.width = 12,
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},
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.m1 = {
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.reg_off = AO_RTC_ALT_CLK_CNTL1,
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.shift = 0,
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.width = 12,
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},
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.m2 = {
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.reg_off = AO_RTC_ALT_CLK_CNTL1,
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.shift = 12,
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.width = 12,
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},
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.dual = {
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.reg_off = AO_RTC_ALT_CLK_CNTL0,
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.shift = 28,
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.width = 1,
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},
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.table = gxbb_32k_div_table,
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},
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.hw.init = &(struct clk_init_data){
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.name = "ao_32k_div",
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.ops = &meson_clk_dualdiv_ops,
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.parent_hws = (const struct clk_hw *[]) { &ao_32k_pre.hw },
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.num_parents = 1,
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},
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};
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static struct clk_regmap ao_32k_sel = {
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.data = &(struct clk_regmap_mux_data) {
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.offset = AO_RTC_ALT_CLK_CNTL1,
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.mask = 0x1,
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.shift = 24,
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.flags = CLK_MUX_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "ao_32k_sel",
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.ops = &clk_regmap_mux_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&ao_32k_div.hw,
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&ao_32k_pre.hw
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},
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.num_parents = 2,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap ao_32k = {
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.data = &(struct clk_regmap_gate_data){
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.offset = AO_RTC_ALT_CLK_CNTL0,
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.bit_idx = 30,
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},
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.hw.init = &(struct clk_init_data){
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.name = "ao_32k",
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.ops = &clk_regmap_gate_ops,
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.parent_hws = (const struct clk_hw *[]) { &ao_32k_sel.hw },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap ao_cts_rtc_oscin = {
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.data = &(struct clk_regmap_mux_data) {
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.offset = AO_RTI_PWR_CNTL_REG0,
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.mask = 0x7,
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.shift = 10,
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.table = (u32[]){ 1, 2, 3, 4 },
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.flags = CLK_MUX_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "ao_cts_rtc_oscin",
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.ops = &clk_regmap_mux_ops,
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.parent_data = (const struct clk_parent_data []) {
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{ .fw_name = "ext-32k-0", },
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{ .fw_name = "ext-32k-1", },
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{ .fw_name = "ext-32k-2", },
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{ .hw = &ao_32k.hw },
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},
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.num_parents = 4,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap ao_clk81 = {
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.data = &(struct clk_regmap_mux_data) {
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.offset = AO_RTI_PWR_CNTL_REG0,
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.mask = 0x1,
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.shift = 0,
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.flags = CLK_MUX_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "ao_clk81",
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.ops = &clk_regmap_mux_ro_ops,
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.parent_data = (const struct clk_parent_data []) {
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{ .fw_name = "mpeg-clk", },
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{ .hw = &ao_cts_rtc_oscin.hw },
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},
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.num_parents = 2,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap ao_cts_cec = {
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.data = &(struct clk_regmap_mux_data) {
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.offset = AO_CRT_CLK_CNTL1,
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.mask = 0x1,
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.shift = 27,
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.flags = CLK_MUX_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data){
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.name = "ao_cts_cec",
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.ops = &clk_regmap_mux_ops,
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/*
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* FIXME: The 'fixme' parent obviously does not exist.
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*
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* ATM, CCF won't call get_parent() if num_parents is 1. It
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* does not allow NULL as a parent name either.
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*
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* On this particular mux, we only know the input #1 parent
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* but, on boot, unknown input #0 is set, so it is critical
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* to call .get_parent() on it
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*
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* Until CCF gets fixed, adding this fake parent that won't
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* ever be registered should work around the problem
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*/
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.parent_data = (const struct clk_parent_data []) {
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{ .name = "fixme", .index = -1, },
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{ .hw = &ao_cts_rtc_oscin.hw },
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},
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.num_parents = 2,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static const unsigned int gxbb_aoclk_reset[] = {
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[RESET_AO_REMOTE] = 16,
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[RESET_AO_I2C_MASTER] = 18,
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[RESET_AO_I2C_SLAVE] = 19,
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[RESET_AO_UART1] = 17,
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[RESET_AO_UART2] = 22,
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[RESET_AO_IR_BLASTER] = 23,
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};
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static struct clk_regmap *gxbb_aoclk[] = {
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&remote_ao,
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&i2c_master_ao,
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&i2c_slave_ao,
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&uart1_ao,
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&uart2_ao,
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&ir_blaster_ao,
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&ao_cts_oscin,
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&ao_32k_pre,
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&ao_32k_div,
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&ao_32k_sel,
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&ao_32k,
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&ao_cts_rtc_oscin,
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&ao_clk81,
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&ao_cts_cec,
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};
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static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
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.hws = {
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[CLKID_AO_REMOTE] = &remote_ao.hw,
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[CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
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[CLKID_AO_I2C_SLAVE] = &i2c_slave_ao.hw,
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[CLKID_AO_UART1] = &uart1_ao.hw,
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[CLKID_AO_UART2] = &uart2_ao.hw,
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[CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw,
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[CLKID_AO_CEC_32K] = &ao_cts_cec.hw,
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[CLKID_AO_CTS_OSCIN] = &ao_cts_oscin.hw,
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[CLKID_AO_32K_PRE] = &ao_32k_pre.hw,
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[CLKID_AO_32K_DIV] = &ao_32k_div.hw,
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[CLKID_AO_32K_SEL] = &ao_32k_sel.hw,
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[CLKID_AO_32K] = &ao_32k.hw,
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[CLKID_AO_CTS_RTC_OSCIN] = &ao_cts_rtc_oscin.hw,
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[CLKID_AO_CLK81] = &ao_clk81.hw,
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},
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.num = NR_CLKS,
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};
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static const struct meson_aoclk_data gxbb_aoclkc_data = {
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.reset_reg = AO_RTI_GEN_CNTL_REG0,
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.num_reset = ARRAY_SIZE(gxbb_aoclk_reset),
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.reset = gxbb_aoclk_reset,
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.num_clks = ARRAY_SIZE(gxbb_aoclk),
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.clks = gxbb_aoclk,
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.hw_data = &gxbb_aoclk_onecell_data,
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};
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static const struct of_device_id gxbb_aoclkc_match_table[] = {
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{
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.compatible = "amlogic,meson-gx-aoclkc",
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.data = &gxbb_aoclkc_data,
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},
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{ }
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};
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MODULE_DEVICE_TABLE(of, gxbb_aoclkc_match_table);
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static struct platform_driver gxbb_aoclkc_driver = {
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.probe = meson_aoclkc_probe,
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.driver = {
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.name = "gxbb-aoclkc",
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.of_match_table = gxbb_aoclkc_match_table,
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},
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};
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module_platform_driver(gxbb_aoclkc_driver);
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MODULE_LICENSE("GPL v2");
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