345 lines
8.6 KiB
C
345 lines
8.6 KiB
C
/*
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* Synopsys AXS10X SDP Generic PLL clock driver
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*
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* Copyright (C) 2017 Synopsys
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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/* PLL registers addresses */
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#define PLL_REG_IDIV 0x0
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#define PLL_REG_FBDIV 0x4
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#define PLL_REG_ODIV 0x8
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/*
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* Bit fields of the PLL IDIV/FBDIV/ODIV registers:
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* ________________________________________________________________________
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* |31 15| 14 | 13 | 12 |11 6|5 0|
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* |-------RESRVED------|-NOUPDATE-|-BYPASS-|-EDGE-|--HIGHTIME--|--LOWTIME--|
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* |____________________|__________|________|______|____________|___________|
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*
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* Following macros determine the way of access to these registers
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* They should be set up only using the macros.
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* reg should be an u32 variable.
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*/
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#define PLL_REG_GET_LOW(reg) \
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(((reg) & (0x3F << 0)) >> 0)
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#define PLL_REG_GET_HIGH(reg) \
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(((reg) & (0x3F << 6)) >> 6)
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#define PLL_REG_GET_EDGE(reg) \
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(((reg) & (BIT(12))) ? 1 : 0)
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#define PLL_REG_GET_BYPASS(reg) \
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(((reg) & (BIT(13))) ? 1 : 0)
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#define PLL_REG_GET_NOUPD(reg) \
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(((reg) & (BIT(14))) ? 1 : 0)
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#define PLL_REG_GET_PAD(reg) \
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(((reg) & (0x1FFFF << 15)) >> 15)
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#define PLL_REG_SET_LOW(reg, value) \
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{ reg |= (((value) & 0x3F) << 0); }
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#define PLL_REG_SET_HIGH(reg, value) \
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{ reg |= (((value) & 0x3F) << 6); }
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#define PLL_REG_SET_EDGE(reg, value) \
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{ reg |= (((value) & 0x01) << 12); }
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#define PLL_REG_SET_BYPASS(reg, value) \
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{ reg |= (((value) & 0x01) << 13); }
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#define PLL_REG_SET_NOUPD(reg, value) \
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{ reg |= (((value) & 0x01) << 14); }
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#define PLL_REG_SET_PAD(reg, value) \
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{ reg |= (((value) & 0x1FFFF) << 15); }
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#define PLL_LOCK BIT(0)
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#define PLL_ERROR BIT(1)
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#define PLL_MAX_LOCK_TIME 100 /* 100 us */
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struct axs10x_pll_cfg {
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u32 rate;
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u32 idiv;
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u32 fbdiv;
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u32 odiv;
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};
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static const struct axs10x_pll_cfg arc_pll_cfg[] = {
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{ 33333333, 1, 1, 1 },
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{ 50000000, 1, 30, 20 },
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{ 75000000, 2, 45, 10 },
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{ 90000000, 2, 54, 10 },
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{ 100000000, 1, 30, 10 },
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{ 125000000, 2, 45, 6 },
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{}
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};
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static const struct axs10x_pll_cfg pgu_pll_cfg[] = {
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{ 25200000, 1, 84, 90 },
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{ 50000000, 1, 100, 54 },
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{ 74250000, 1, 44, 16 },
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{}
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};
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struct axs10x_pll_clk {
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struct clk_hw hw;
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void __iomem *base;
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void __iomem *lock;
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const struct axs10x_pll_cfg *pll_cfg;
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struct device *dev;
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};
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static inline void axs10x_pll_write(struct axs10x_pll_clk *clk, u32 reg,
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u32 val)
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{
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iowrite32(val, clk->base + reg);
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}
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static inline u32 axs10x_pll_read(struct axs10x_pll_clk *clk, u32 reg)
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{
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return ioread32(clk->base + reg);
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}
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static inline struct axs10x_pll_clk *to_axs10x_pll_clk(struct clk_hw *hw)
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{
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return container_of(hw, struct axs10x_pll_clk, hw);
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}
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static inline u32 axs10x_div_get_value(u32 reg)
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{
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if (PLL_REG_GET_BYPASS(reg))
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return 1;
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return PLL_REG_GET_HIGH(reg) + PLL_REG_GET_LOW(reg);
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}
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static inline u32 axs10x_encode_div(unsigned int id, int upd)
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{
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u32 div = 0;
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PLL_REG_SET_LOW(div, (id % 2 == 0) ? id >> 1 : (id >> 1) + 1);
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PLL_REG_SET_HIGH(div, id >> 1);
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PLL_REG_SET_EDGE(div, id % 2);
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PLL_REG_SET_BYPASS(div, id == 1 ? 1 : 0);
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PLL_REG_SET_NOUPD(div, upd == 0 ? 1 : 0);
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return div;
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}
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static unsigned long axs10x_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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u64 rate;
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u32 idiv, fbdiv, odiv;
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struct axs10x_pll_clk *clk = to_axs10x_pll_clk(hw);
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idiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_IDIV));
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fbdiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_FBDIV));
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odiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_ODIV));
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rate = (u64)parent_rate * fbdiv;
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do_div(rate, idiv * odiv);
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return rate;
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}
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static long axs10x_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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int i;
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long best_rate;
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struct axs10x_pll_clk *clk = to_axs10x_pll_clk(hw);
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const struct axs10x_pll_cfg *pll_cfg = clk->pll_cfg;
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if (pll_cfg[0].rate == 0)
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return -EINVAL;
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best_rate = pll_cfg[0].rate;
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for (i = 1; pll_cfg[i].rate != 0; i++) {
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if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate))
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best_rate = pll_cfg[i].rate;
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}
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return best_rate;
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}
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static int axs10x_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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int i;
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struct axs10x_pll_clk *clk = to_axs10x_pll_clk(hw);
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const struct axs10x_pll_cfg *pll_cfg = clk->pll_cfg;
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for (i = 0; pll_cfg[i].rate != 0; i++) {
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if (pll_cfg[i].rate == rate) {
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axs10x_pll_write(clk, PLL_REG_IDIV,
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axs10x_encode_div(pll_cfg[i].idiv, 0));
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axs10x_pll_write(clk, PLL_REG_FBDIV,
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axs10x_encode_div(pll_cfg[i].fbdiv, 0));
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axs10x_pll_write(clk, PLL_REG_ODIV,
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axs10x_encode_div(pll_cfg[i].odiv, 1));
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/*
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* Wait until CGU relocks and check error status.
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* If after timeout CGU is unlocked yet return error
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*/
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udelay(PLL_MAX_LOCK_TIME);
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if (!(ioread32(clk->lock) & PLL_LOCK))
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return -ETIMEDOUT;
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if (ioread32(clk->lock) & PLL_ERROR)
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return -EINVAL;
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return 0;
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}
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}
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dev_err(clk->dev, "invalid rate=%ld, parent_rate=%ld\n", rate,
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parent_rate);
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return -EINVAL;
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}
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static const struct clk_ops axs10x_pll_ops = {
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.recalc_rate = axs10x_pll_recalc_rate,
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.round_rate = axs10x_pll_round_rate,
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.set_rate = axs10x_pll_set_rate,
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};
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static int axs10x_pll_clk_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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const char *parent_name;
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struct axs10x_pll_clk *pll_clk;
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struct clk_init_data init = { };
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int ret;
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pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);
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if (!pll_clk)
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return -ENOMEM;
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pll_clk->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(pll_clk->base))
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return PTR_ERR(pll_clk->base);
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pll_clk->lock = devm_platform_ioremap_resource(pdev, 1);
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if (IS_ERR(pll_clk->lock))
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return PTR_ERR(pll_clk->lock);
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init.name = dev->of_node->name;
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init.ops = &axs10x_pll_ops;
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parent_name = of_clk_get_parent_name(dev->of_node, 0);
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init.parent_names = &parent_name;
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init.num_parents = 1;
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pll_clk->hw.init = &init;
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pll_clk->dev = dev;
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pll_clk->pll_cfg = of_device_get_match_data(dev);
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if (!pll_clk->pll_cfg) {
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dev_err(dev, "No OF match data provided\n");
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return -EINVAL;
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}
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ret = devm_clk_hw_register(dev, &pll_clk->hw);
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if (ret) {
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dev_err(dev, "failed to register %s clock\n", init.name);
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return ret;
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}
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return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get,
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&pll_clk->hw);
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}
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static int axs10x_pll_clk_remove(struct platform_device *pdev)
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{
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of_clk_del_provider(pdev->dev.of_node);
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return 0;
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}
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static void __init of_axs10x_pll_clk_setup(struct device_node *node)
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{
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const char *parent_name;
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struct axs10x_pll_clk *pll_clk;
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struct clk_init_data init = { };
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int ret;
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pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
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if (!pll_clk)
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return;
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pll_clk->base = of_iomap(node, 0);
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if (!pll_clk->base) {
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pr_err("failed to map pll div registers\n");
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goto err_free_pll_clk;
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}
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pll_clk->lock = of_iomap(node, 1);
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if (!pll_clk->lock) {
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pr_err("failed to map pll lock register\n");
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goto err_unmap_base;
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}
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init.name = node->name;
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init.ops = &axs10x_pll_ops;
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parent_name = of_clk_get_parent_name(node, 0);
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init.parent_names = &parent_name;
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init.num_parents = parent_name ? 1 : 0;
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pll_clk->hw.init = &init;
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pll_clk->pll_cfg = arc_pll_cfg;
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ret = clk_hw_register(NULL, &pll_clk->hw);
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if (ret) {
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pr_err("failed to register %pOFn clock\n", node);
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goto err_unmap_lock;
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}
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ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clk->hw);
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if (ret) {
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pr_err("failed to add hw provider for %pOFn clock\n", node);
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goto err_unregister_clk;
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}
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return;
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err_unregister_clk:
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clk_hw_unregister(&pll_clk->hw);
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err_unmap_lock:
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iounmap(pll_clk->lock);
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err_unmap_base:
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iounmap(pll_clk->base);
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err_free_pll_clk:
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kfree(pll_clk);
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}
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CLK_OF_DECLARE(axs10x_pll_clock, "snps,axs10x-arc-pll-clock",
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of_axs10x_pll_clk_setup);
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static const struct of_device_id axs10x_pll_clk_id[] = {
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{ .compatible = "snps,axs10x-pgu-pll-clock", .data = &pgu_pll_cfg},
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{ }
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};
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MODULE_DEVICE_TABLE(of, axs10x_pll_clk_id);
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static struct platform_driver axs10x_pll_clk_driver = {
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.driver = {
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.name = "axs10x-pll-clock",
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.of_match_table = axs10x_pll_clk_id,
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},
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.probe = axs10x_pll_clk_probe,
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.remove = axs10x_pll_clk_remove,
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};
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builtin_platform_driver(axs10x_pll_clk_driver);
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MODULE_AUTHOR("Vlad Zakharov <vzakhar@synopsys.com>");
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MODULE_DESCRIPTION("Synopsys AXS10X SDP Generic PLL Clock Driver");
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MODULE_LICENSE("GPL v2");
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