347 lines
10 KiB
C
347 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __POWERNV_PCI_H
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#define __POWERNV_PCI_H
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#include <linux/compiler.h> /* for __printf */
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#include <linux/iommu.h>
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#include <asm/iommu.h>
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#include <asm/msi_bitmap.h>
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struct pci_dn;
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enum pnv_phb_type {
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PNV_PHB_IODA1,
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PNV_PHB_IODA2,
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PNV_PHB_NPU_OCAPI,
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};
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/* Precise PHB model for error management */
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enum pnv_phb_model {
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PNV_PHB_MODEL_UNKNOWN,
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PNV_PHB_MODEL_P7IOC,
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PNV_PHB_MODEL_PHB3,
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};
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#define PNV_PCI_DIAG_BUF_SIZE 8192
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#define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
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#define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
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#define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
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#define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */
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#define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */
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#define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */
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/*
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* A brief note on PNV_IODA_PE_BUS_ALL
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*
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* This is needed because of the behaviour of PCIe-to-PCI bridges. The PHB uses
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* the Requester ID field of the PCIe request header to determine the device
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* (and PE) that initiated a DMA. In legacy PCI individual memory read/write
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* requests aren't tagged with the RID. To work around this the PCIe-to-PCI
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* bridge will use (secondary_bus_no << 8) | 0x00 as the RID on the PCIe side.
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*
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* PCIe-to-X bridges have a similar issue even though PCI-X requests also have
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* a RID in the transaction header. The PCIe-to-X bridge is permitted to "take
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* ownership" of a transaction by a PCI-X device when forwarding it to the PCIe
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* side of the bridge.
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*
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* To work around these problems we use the BUS_ALL flag since every subordinate
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* bus of the bridge should go into the same PE.
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*/
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/* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */
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#define PNV_IODA_STOPPED_STATE 0x8000000000000000
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/* Data associated with a PE, including IOMMU tracking etc.. */
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struct pnv_phb;
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struct pnv_ioda_pe {
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unsigned long flags;
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struct pnv_phb *phb;
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int device_count;
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/* A PE can be associated with a single device or an
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* entire bus (& children). In the former case, pdev
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* is populated, in the later case, pbus is.
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*/
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#ifdef CONFIG_PCI_IOV
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struct pci_dev *parent_dev;
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#endif
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struct pci_dev *pdev;
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struct pci_bus *pbus;
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/* Effective RID (device RID for a device PE and base bus
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* RID with devfn 0 for a bus PE)
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*/
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unsigned int rid;
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/* PE number */
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unsigned int pe_number;
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/* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
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struct iommu_table_group table_group;
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/* 64-bit TCE bypass region */
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bool tce_bypass_enabled;
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uint64_t tce_bypass_base;
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/*
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* Used to track whether we've done DMA setup for this PE or not. We
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* want to defer allocating TCE tables, etc until we've added a
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* non-bridge device to the PE.
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*/
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bool dma_setup_done;
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/* MSIs. MVE index is identical for 32 and 64 bit MSI
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* and -1 if not supported. (It's actually identical to the
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* PE number)
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*/
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int mve_number;
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/* PEs in compound case */
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struct pnv_ioda_pe *master;
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struct list_head slaves;
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/* Link in list of PE#s */
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struct list_head list;
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};
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#define PNV_PHB_FLAG_EEH (1 << 0)
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struct pnv_phb {
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struct pci_controller *hose;
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enum pnv_phb_type type;
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enum pnv_phb_model model;
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u64 hub_id;
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u64 opal_id;
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int flags;
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void __iomem *regs;
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u64 regs_phys;
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spinlock_t lock;
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#ifdef CONFIG_DEBUG_FS
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int has_dbgfs;
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struct dentry *dbgfs;
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#endif
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unsigned int msi_base;
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struct msi_bitmap msi_bmp;
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int (*init_m64)(struct pnv_phb *phb);
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int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
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void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
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int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);
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struct {
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/* Global bridge info */
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unsigned int total_pe_num;
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unsigned int reserved_pe_idx;
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unsigned int root_pe_idx;
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/* 32-bit MMIO window */
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unsigned int m32_size;
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unsigned int m32_segsize;
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unsigned int m32_pci_base;
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/* 64-bit MMIO window */
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unsigned int m64_bar_idx;
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unsigned long m64_size;
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unsigned long m64_segsize;
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unsigned long m64_base;
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#define MAX_M64_BARS 64
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unsigned long m64_bar_alloc;
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/* IO ports */
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unsigned int io_size;
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unsigned int io_segsize;
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unsigned int io_pci_base;
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/* PE allocation */
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struct mutex pe_alloc_mutex;
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unsigned long *pe_alloc;
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struct pnv_ioda_pe *pe_array;
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/* M32 & IO segment maps */
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unsigned int *m64_segmap;
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unsigned int *m32_segmap;
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unsigned int *io_segmap;
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/* DMA32 segment maps - IODA1 only */
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unsigned int dma32_count;
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unsigned int *dma32_segmap;
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/* IRQ chip */
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int irq_chip_init;
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struct irq_chip irq_chip;
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/* Sorted list of used PE's based
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* on the sequence of creation
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*/
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struct list_head pe_list;
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struct mutex pe_list_mutex;
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/* Reverse map of PEs, indexed by {bus, devfn} */
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unsigned int pe_rmap[0x10000];
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} ioda;
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/* PHB and hub diagnostics */
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unsigned int diag_data_size;
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u8 *diag_data;
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};
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/* IODA PE management */
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static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r)
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{
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/*
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* WARNING: We cannot rely on the resource flags. The Linux PCI
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* allocation code sometimes decides to put a 64-bit prefetchable
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* BAR in the 32-bit window, so we have to compare the addresses.
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*
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* For simplicity we only test resource start.
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*/
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return (r->start >= phb->ioda.m64_base &&
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r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
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}
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static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags)
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{
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unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
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return (resource_flags & flags) == flags;
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}
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int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe);
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int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe);
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void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe);
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void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe);
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struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb, int count);
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void pnv_ioda_free_pe(struct pnv_ioda_pe *pe);
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#ifdef CONFIG_PCI_IOV
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/*
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* For SR-IOV we want to put each VF's MMIO resource in to a separate PE.
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* This requires a bit of acrobatics with the MMIO -> PE configuration
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* and this structure is used to keep track of it all.
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*/
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struct pnv_iov_data {
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/* number of VFs enabled */
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u16 num_vfs;
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/* pointer to the array of VF PEs. num_vfs long*/
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struct pnv_ioda_pe *vf_pe_arr;
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/* Did we map the VF BAR with single-PE IODA BARs? */
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bool m64_single_mode[PCI_SRIOV_NUM_BARS];
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/*
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* True if we're using any segmented windows. In that case we need
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* shift the start of the IOV resource the segment corresponding to
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* the allocated PE.
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*/
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bool need_shift;
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/*
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* Bit mask used to track which m64 windows are used to map the
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* SR-IOV BARs for this device.
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*/
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DECLARE_BITMAP(used_m64_bar_mask, MAX_M64_BARS);
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/*
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* If we map the SR-IOV BARs with a segmented window then
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* parts of that window will be "claimed" by other PEs.
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*
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* "holes" here is used to reserve the leading portion
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* of the window that is used by other (non VF) PEs.
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*/
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struct resource holes[PCI_SRIOV_NUM_BARS];
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};
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static inline struct pnv_iov_data *pnv_iov_get(struct pci_dev *pdev)
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{
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return pdev->dev.archdata.iov_data;
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}
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void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev);
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resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, int resno);
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int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
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int pnv_pcibios_sriov_disable(struct pci_dev *pdev);
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#endif /* CONFIG_PCI_IOV */
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extern struct pci_ops pnv_pci_ops;
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void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
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unsigned char *log_buff);
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int pnv_pci_cfg_read(struct pci_dn *pdn,
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int where, int size, u32 *val);
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int pnv_pci_cfg_write(struct pci_dn *pdn,
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int where, int size, u32 val);
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extern struct iommu_table *pnv_pci_table_alloc(int nid);
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extern void pnv_pci_init_ioda_hub(struct device_node *np);
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extern void pnv_pci_init_ioda2_phb(struct device_node *np);
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extern void pnv_pci_init_npu2_opencapi_phb(struct device_node *np);
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extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
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extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
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extern struct pnv_ioda_pe *pnv_pci_bdfn_to_pe(struct pnv_phb *phb, u16 bdfn);
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extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev);
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extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq);
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extern unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
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__u64 window_size, __u32 levels);
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extern int pnv_eeh_post_init(void);
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__printf(3, 4)
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extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
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const char *fmt, ...);
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#define pe_err(pe, fmt, ...) \
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pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
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#define pe_warn(pe, fmt, ...) \
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pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
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#define pe_info(pe, fmt, ...) \
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pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
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/* pci-ioda-tce.c */
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#define POWERNV_IOMMU_DEFAULT_LEVELS 2
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#define POWERNV_IOMMU_MAX_LEVELS 5
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extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
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unsigned long uaddr, enum dma_data_direction direction,
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unsigned long attrs);
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extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages);
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extern int pnv_tce_xchg(struct iommu_table *tbl, long index,
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unsigned long *hpa, enum dma_data_direction *direction,
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bool alloc);
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extern __be64 *pnv_tce_useraddrptr(struct iommu_table *tbl, long index,
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bool alloc);
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extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index);
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extern long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
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__u32 page_shift, __u64 window_size, __u32 levels,
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bool alloc_userspace_copy, struct iommu_table *tbl);
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extern void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
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extern long pnv_pci_link_table_and_group(int node, int num,
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struct iommu_table *tbl,
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struct iommu_table_group *table_group);
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extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
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struct iommu_table_group *table_group);
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extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
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void *tce_mem, u64 tce_size,
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u64 dma_offset, unsigned int page_shift);
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extern unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb);
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static inline struct pnv_phb *pci_bus_to_pnvhb(struct pci_bus *bus)
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{
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struct pci_controller *hose = bus->sysdata;
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if (hose)
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return hose->private_data;
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return NULL;
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}
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#endif /* __POWERNV_PCI_H */
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