456 lines
10 KiB
C
456 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2006-2007 PA Semi, Inc
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*
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* Authors: Kip Walker, PA Semi
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* Olof Johansson, PA Semi
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*
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* Maintained by: Olof Johansson <olof@lixom.net>
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*
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* Based on arch/powerpc/platforms/maple/setup.c
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*/
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/console.h>
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#include <linux/export.h>
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#include <linux/pci.h>
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#include <linux/of_platform.h>
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#include <linux/gfp.h>
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#include <asm/prom.h>
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#include <asm/iommu.h>
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#include <asm/machdep.h>
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#include <asm/i8259.h>
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#include <asm/mpic.h>
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#include <asm/smp.h>
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#include <asm/time.h>
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#include <asm/mmu.h>
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#include <asm/debug.h>
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#include <pcmcia/ss.h>
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#include <pcmcia/cistpl.h>
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#include <pcmcia/ds.h>
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#include "pasemi.h"
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/* SDC reset register, must be pre-mapped at reset time */
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static void __iomem *reset_reg;
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/* Various error status registers, must be pre-mapped at MCE time */
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#define MAX_MCE_REGS 32
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struct mce_regs {
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char *name;
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void __iomem *addr;
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};
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static struct mce_regs mce_regs[MAX_MCE_REGS];
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static int num_mce_regs;
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static int nmi_virq = 0;
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static void __noreturn pas_restart(char *cmd)
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{
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/* Need to put others cpu in hold loop so they're not sleeping */
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smp_send_stop();
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udelay(10000);
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printk("Restarting...\n");
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while (1)
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out_le32(reset_reg, 0x6000000);
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}
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#ifdef CONFIG_PPC_PASEMI_NEMO
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void pas_shutdown(void)
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{
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/* Set the PLD bit that makes the SB600 think the power button is being pressed */
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void __iomem *pld_map = ioremap(0xf5000000,4096);
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while (1)
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out_8(pld_map+7,0x01);
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}
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/* RTC platform device structure as is not in device tree */
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static struct resource rtc_resource[] = {{
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.name = "rtc",
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.start = 0x70,
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.end = 0x71,
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.flags = IORESOURCE_IO,
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}, {
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.name = "rtc",
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.start = 8,
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.end = 8,
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.flags = IORESOURCE_IRQ,
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}};
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static inline void nemo_init_rtc(void)
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{
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platform_device_register_simple("rtc_cmos", -1, rtc_resource, 2);
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}
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#else
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static inline void nemo_init_rtc(void)
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{
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}
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#endif
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#ifdef CONFIG_SMP
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static arch_spinlock_t timebase_lock;
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static unsigned long timebase;
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static void pas_give_timebase(void)
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{
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unsigned long flags;
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local_irq_save(flags);
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hard_irq_disable();
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arch_spin_lock(&timebase_lock);
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mtspr(SPRN_TBCTL, TBCTL_FREEZE);
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isync();
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timebase = get_tb();
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arch_spin_unlock(&timebase_lock);
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while (timebase)
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barrier();
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mtspr(SPRN_TBCTL, TBCTL_RESTART);
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local_irq_restore(flags);
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}
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static void pas_take_timebase(void)
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{
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while (!timebase)
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smp_rmb();
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arch_spin_lock(&timebase_lock);
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set_tb(timebase >> 32, timebase & 0xffffffff);
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timebase = 0;
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arch_spin_unlock(&timebase_lock);
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}
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static struct smp_ops_t pas_smp_ops = {
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.probe = smp_mpic_probe,
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.message_pass = smp_mpic_message_pass,
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.kick_cpu = smp_generic_kick_cpu,
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.setup_cpu = smp_mpic_setup_cpu,
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.give_timebase = pas_give_timebase,
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.take_timebase = pas_take_timebase,
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};
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#endif /* CONFIG_SMP */
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static void __init pas_setup_arch(void)
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{
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#ifdef CONFIG_SMP
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/* Setup SMP callback */
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smp_ops = &pas_smp_ops;
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#endif
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/* Remap SDC register for doing reset */
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/* XXXOJN This should maybe come out of the device tree */
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reset_reg = ioremap(0xfc101100, 4);
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}
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static int __init pas_setup_mce_regs(void)
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{
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struct pci_dev *dev;
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int reg;
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/* Remap various SoC status registers for use by the MCE handler */
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reg = 0;
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dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, NULL);
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while (dev && reg < MAX_MCE_REGS) {
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mce_regs[reg].name = kasprintf(GFP_KERNEL,
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"mc%d_mcdebug_errsta", reg);
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mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x730);
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dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, dev);
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reg++;
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}
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dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
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if (dev && reg+4 < MAX_MCE_REGS) {
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mce_regs[reg].name = "iobdbg_IntStatus1";
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mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x438);
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reg++;
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mce_regs[reg].name = "iobdbg_IOCTbusIntDbgReg";
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mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x454);
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reg++;
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mce_regs[reg].name = "iobiom_IntStatus";
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mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc10);
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reg++;
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mce_regs[reg].name = "iobiom_IntDbgReg";
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mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc1c);
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reg++;
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}
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dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa009, NULL);
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if (dev && reg+2 < MAX_MCE_REGS) {
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mce_regs[reg].name = "l2csts_IntStatus";
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mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x200);
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reg++;
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mce_regs[reg].name = "l2csts_Cnt";
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mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x214);
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reg++;
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}
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num_mce_regs = reg;
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return 0;
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}
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machine_device_initcall(pasemi, pas_setup_mce_regs);
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#ifdef CONFIG_PPC_PASEMI_NEMO
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static void sb600_8259_cascade(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned int cascade_irq = i8259_irq();
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if (cascade_irq)
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generic_handle_irq(cascade_irq);
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chip->irq_eoi(&desc->irq_data);
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}
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static void __init nemo_init_IRQ(struct mpic *mpic)
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{
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struct device_node *np;
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int gpio_virq;
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/* Connect the SB600's legacy i8259 controller */
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np = of_find_node_by_path("/pxp@0,e0000000");
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i8259_init(np, 0);
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of_node_put(np);
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gpio_virq = irq_create_mapping(NULL, 3);
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irq_set_irq_type(gpio_virq, IRQ_TYPE_LEVEL_HIGH);
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irq_set_chained_handler(gpio_virq, sb600_8259_cascade);
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mpic_unmask_irq(irq_get_irq_data(gpio_virq));
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irq_set_default_host(mpic->irqhost);
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}
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#else
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static inline void nemo_init_IRQ(struct mpic *mpic)
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{
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}
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#endif
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static __init void pas_init_IRQ(void)
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{
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struct device_node *np;
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struct device_node *root, *mpic_node;
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unsigned long openpic_addr;
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const unsigned int *opprop;
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int naddr, opplen;
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int mpic_flags;
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const unsigned int *nmiprop;
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struct mpic *mpic;
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mpic_node = NULL;
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for_each_node_by_type(np, "interrupt-controller")
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if (of_device_is_compatible(np, "open-pic")) {
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mpic_node = np;
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break;
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}
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if (!mpic_node)
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for_each_node_by_type(np, "open-pic") {
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mpic_node = np;
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break;
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}
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if (!mpic_node) {
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pr_err("Failed to locate the MPIC interrupt controller\n");
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return;
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}
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/* Find address list in /platform-open-pic */
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root = of_find_node_by_path("/");
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naddr = of_n_addr_cells(root);
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opprop = of_get_property(root, "platform-open-pic", &opplen);
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if (!opprop) {
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pr_err("No platform-open-pic property.\n");
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of_node_put(root);
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return;
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}
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openpic_addr = of_read_number(opprop, naddr);
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pr_debug("OpenPIC addr: %lx\n", openpic_addr);
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mpic_flags = MPIC_LARGE_VECTORS | MPIC_NO_BIAS | MPIC_NO_RESET;
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nmiprop = of_get_property(mpic_node, "nmi-source", NULL);
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if (nmiprop)
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mpic_flags |= MPIC_ENABLE_MCK;
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mpic = mpic_alloc(mpic_node, openpic_addr,
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mpic_flags, 0, 0, "PASEMI-OPIC");
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BUG_ON(!mpic);
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mpic_assign_isu(mpic, 0, mpic->paddr + 0x10000);
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mpic_init(mpic);
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/* The NMI/MCK source needs to be prio 15 */
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if (nmiprop) {
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nmi_virq = irq_create_mapping(NULL, *nmiprop);
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mpic_irq_set_priority(nmi_virq, 15);
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irq_set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING);
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mpic_unmask_irq(irq_get_irq_data(nmi_virq));
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}
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nemo_init_IRQ(mpic);
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of_node_put(mpic_node);
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of_node_put(root);
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}
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static void __init pas_progress(char *s, unsigned short hex)
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{
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printk("[%04x] : %s\n", hex, s ? s : "");
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}
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static int pas_machine_check_handler(struct pt_regs *regs)
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{
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int cpu = smp_processor_id();
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unsigned long srr0, srr1, dsisr;
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int dump_slb = 0;
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int i;
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srr0 = regs->nip;
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srr1 = regs->msr;
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if (nmi_virq && mpic_get_mcirq() == nmi_virq) {
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pr_err("NMI delivered\n");
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debugger(regs);
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mpic_end_irq(irq_get_irq_data(nmi_virq));
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goto out;
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}
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dsisr = mfspr(SPRN_DSISR);
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pr_err("Machine Check on CPU %d\n", cpu);
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pr_err("SRR0 0x%016lx SRR1 0x%016lx\n", srr0, srr1);
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pr_err("DSISR 0x%016lx DAR 0x%016lx\n", dsisr, regs->dar);
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pr_err("BER 0x%016lx MER 0x%016lx\n", mfspr(SPRN_PA6T_BER),
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mfspr(SPRN_PA6T_MER));
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pr_err("IER 0x%016lx DER 0x%016lx\n", mfspr(SPRN_PA6T_IER),
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mfspr(SPRN_PA6T_DER));
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pr_err("Cause:\n");
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if (srr1 & 0x200000)
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pr_err("Signalled by SDC\n");
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if (srr1 & 0x100000) {
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pr_err("Load/Store detected error:\n");
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if (dsisr & 0x8000)
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pr_err("D-cache ECC double-bit error or bus error\n");
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if (dsisr & 0x4000)
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pr_err("LSU snoop response error\n");
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if (dsisr & 0x2000) {
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pr_err("MMU SLB multi-hit or invalid B field\n");
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dump_slb = 1;
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}
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if (dsisr & 0x1000)
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pr_err("Recoverable Duptags\n");
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if (dsisr & 0x800)
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pr_err("Recoverable D-cache parity error count overflow\n");
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if (dsisr & 0x400)
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pr_err("TLB parity error count overflow\n");
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}
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if (srr1 & 0x80000)
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pr_err("Bus Error\n");
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if (srr1 & 0x40000) {
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pr_err("I-side SLB multiple hit\n");
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dump_slb = 1;
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}
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if (srr1 & 0x20000)
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pr_err("I-cache parity error hit\n");
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if (num_mce_regs == 0)
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pr_err("No MCE registers mapped yet, can't dump\n");
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else
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pr_err("SoC debug registers:\n");
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for (i = 0; i < num_mce_regs; i++)
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pr_err("%s: 0x%08x\n", mce_regs[i].name,
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in_le32(mce_regs[i].addr));
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if (dump_slb) {
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unsigned long e, v;
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int i;
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pr_err("slb contents:\n");
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for (i = 0; i < mmu_slb_size; i++) {
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asm volatile("slbmfee %0,%1" : "=r" (e) : "r" (i));
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asm volatile("slbmfev %0,%1" : "=r" (v) : "r" (i));
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pr_err("%02d %016lx %016lx\n", i, e, v);
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}
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}
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out:
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/* SRR1[62] is from MSR[62] if recoverable, so pass that back */
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return !!(srr1 & 0x2);
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}
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static const struct of_device_id pasemi_bus_ids[] = {
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/* Unfortunately needed for legacy firmwares */
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{ .type = "localbus", },
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{ .type = "sdc", },
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/* These are the proper entries, which newer firmware uses */
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{ .compatible = "pasemi,localbus", },
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{ .compatible = "pasemi,sdc", },
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{},
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};
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static int __init pasemi_publish_devices(void)
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{
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/* Publish OF platform devices for SDC and other non-PCI devices */
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of_platform_bus_probe(NULL, pasemi_bus_ids, NULL);
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nemo_init_rtc();
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return 0;
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}
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machine_device_initcall(pasemi, pasemi_publish_devices);
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/*
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* Called very early, MMU is off, device-tree isn't unflattened
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*/
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static int __init pas_probe(void)
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{
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if (!of_machine_is_compatible("PA6T-1682M") &&
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!of_machine_is_compatible("pasemi,pwrficient"))
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return 0;
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#ifdef CONFIG_PPC_PASEMI_NEMO
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/*
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* Check for the Nemo motherboard here, if we are running on one
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* change the machine definition to fit
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*/
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if (of_machine_is_compatible("pasemi,nemo")) {
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pm_power_off = pas_shutdown;
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ppc_md.name = "A-EON Amigaone X1000";
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}
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#endif
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iommu_init_early_pasemi();
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return 1;
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}
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define_machine(pasemi) {
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.name = "PA Semi PWRficient",
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.probe = pas_probe,
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.setup_arch = pas_setup_arch,
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.discover_phbs = pas_pci_init,
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.init_IRQ = pas_init_IRQ,
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.get_irq = mpic_get_irq,
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.restart = pas_restart,
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.get_boot_time = pas_get_boot_time,
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.calibrate_decr = generic_calibrate_decr,
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.progress = pas_progress,
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.machine_check_exception = pas_machine_check_handler,
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};
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