299 lines
7.6 KiB
C
299 lines
7.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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#include <linux/regset.h>
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#include <linux/hw_breakpoint.h>
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#include <asm/debug.h>
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#include "ptrace-decl.h"
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void user_enable_single_step(struct task_struct *task)
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{
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struct pt_regs *regs = task->thread.regs;
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if (regs != NULL)
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regs_set_return_msr(regs, (regs->msr & ~MSR_BE) | MSR_SE);
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set_tsk_thread_flag(task, TIF_SINGLESTEP);
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}
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void user_enable_block_step(struct task_struct *task)
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{
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struct pt_regs *regs = task->thread.regs;
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if (regs != NULL)
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regs_set_return_msr(regs, (regs->msr & ~MSR_SE) | MSR_BE);
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set_tsk_thread_flag(task, TIF_SINGLESTEP);
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}
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void user_disable_single_step(struct task_struct *task)
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{
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struct pt_regs *regs = task->thread.regs;
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if (regs != NULL)
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regs_set_return_msr(regs, regs->msr & ~(MSR_SE | MSR_BE));
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clear_tsk_thread_flag(task, TIF_SINGLESTEP);
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}
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void ppc_gethwdinfo(struct ppc_debug_info *dbginfo)
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{
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dbginfo->version = 1;
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dbginfo->num_instruction_bps = 0;
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if (ppc_breakpoint_available())
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dbginfo->num_data_bps = nr_wp_slots();
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else
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dbginfo->num_data_bps = 0;
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dbginfo->num_condition_regs = 0;
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dbginfo->data_bp_alignment = sizeof(long);
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dbginfo->sizeof_condition = 0;
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if (IS_ENABLED(CONFIG_HAVE_HW_BREAKPOINT)) {
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dbginfo->features = PPC_DEBUG_FEATURE_DATA_BP_RANGE;
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if (dawr_enabled())
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dbginfo->features |= PPC_DEBUG_FEATURE_DATA_BP_DAWR;
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} else {
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dbginfo->features = 0;
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}
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if (cpu_has_feature(CPU_FTR_ARCH_31))
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dbginfo->features |= PPC_DEBUG_FEATURE_DATA_BP_ARCH_31;
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}
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int ptrace_get_debugreg(struct task_struct *child, unsigned long addr,
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unsigned long __user *datalp)
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{
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unsigned long dabr_fake;
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/* We only support one DABR and no IABRS at the moment */
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if (addr > 0)
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return -EINVAL;
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dabr_fake = ((child->thread.hw_brk[0].address & (~HW_BRK_TYPE_DABR)) |
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(child->thread.hw_brk[0].type & HW_BRK_TYPE_DABR));
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return put_user(dabr_fake, datalp);
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}
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/*
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* ptrace_set_debugreg() fakes DABR and DABR is only one. So even if
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* internal hw supports more than one watchpoint, we support only one
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* watchpoint with this interface.
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*/
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int ptrace_set_debugreg(struct task_struct *task, unsigned long addr, unsigned long data)
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{
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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int ret;
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struct thread_struct *thread = &task->thread;
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struct perf_event *bp;
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struct perf_event_attr attr;
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#endif /* CONFIG_HAVE_HW_BREAKPOINT */
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bool set_bp = true;
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struct arch_hw_breakpoint hw_brk;
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/* For ppc64 we support one DABR and no IABR's at the moment (ppc64).
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* For embedded processors we support one DAC and no IAC's at the
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* moment.
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*/
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if (addr > 0)
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return -EINVAL;
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/* The bottom 3 bits in dabr are flags */
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if ((data & ~0x7UL) >= TASK_SIZE)
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return -EIO;
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/* For processors using DABR (i.e. 970), the bottom 3 bits are flags.
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* It was assumed, on previous implementations, that 3 bits were
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* passed together with the data address, fitting the design of the
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* DABR register, as follows:
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*
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* bit 0: Read flag
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* bit 1: Write flag
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* bit 2: Breakpoint translation
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*
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* Thus, we use them here as so.
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*/
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/* Ensure breakpoint translation bit is set */
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if (data && !(data & HW_BRK_TYPE_TRANSLATE))
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return -EIO;
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hw_brk.address = data & (~HW_BRK_TYPE_DABR);
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hw_brk.type = (data & HW_BRK_TYPE_DABR) | HW_BRK_TYPE_PRIV_ALL;
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hw_brk.len = DABR_MAX_LEN;
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hw_brk.hw_len = DABR_MAX_LEN;
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set_bp = (data) && (hw_brk.type & HW_BRK_TYPE_RDWR);
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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bp = thread->ptrace_bps[0];
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if (!set_bp) {
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if (bp) {
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unregister_hw_breakpoint(bp);
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thread->ptrace_bps[0] = NULL;
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}
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return 0;
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}
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if (bp) {
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attr = bp->attr;
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attr.bp_addr = hw_brk.address;
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attr.bp_len = DABR_MAX_LEN;
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arch_bp_generic_fields(hw_brk.type, &attr.bp_type);
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/* Enable breakpoint */
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attr.disabled = false;
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ret = modify_user_hw_breakpoint(bp, &attr);
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if (ret)
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return ret;
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thread->ptrace_bps[0] = bp;
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thread->hw_brk[0] = hw_brk;
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return 0;
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}
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/* Create a new breakpoint request if one doesn't exist already */
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hw_breakpoint_init(&attr);
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attr.bp_addr = hw_brk.address;
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attr.bp_len = DABR_MAX_LEN;
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arch_bp_generic_fields(hw_brk.type,
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&attr.bp_type);
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thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr,
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ptrace_triggered, NULL, task);
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if (IS_ERR(bp)) {
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thread->ptrace_bps[0] = NULL;
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return PTR_ERR(bp);
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}
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#else /* !CONFIG_HAVE_HW_BREAKPOINT */
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if (set_bp && (!ppc_breakpoint_available()))
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return -ENODEV;
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#endif /* CONFIG_HAVE_HW_BREAKPOINT */
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task->thread.hw_brk[0] = hw_brk;
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return 0;
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}
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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static int find_empty_ptrace_bp(struct thread_struct *thread)
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{
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int i;
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for (i = 0; i < nr_wp_slots(); i++) {
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if (!thread->ptrace_bps[i])
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return i;
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}
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return -1;
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}
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#endif
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static int find_empty_hw_brk(struct thread_struct *thread)
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{
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int i;
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for (i = 0; i < nr_wp_slots(); i++) {
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if (!thread->hw_brk[i].address)
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return i;
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}
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return -1;
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}
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long ppc_set_hwdebug(struct task_struct *child, struct ppc_hw_breakpoint *bp_info)
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{
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int i;
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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int len = 0;
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struct thread_struct *thread = &child->thread;
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struct perf_event *bp;
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struct perf_event_attr attr;
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#endif /* CONFIG_HAVE_HW_BREAKPOINT */
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struct arch_hw_breakpoint brk;
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if (bp_info->version != 1)
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return -ENOTSUPP;
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/*
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* We only support one data breakpoint
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*/
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if ((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0 ||
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(bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0 ||
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bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
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return -EINVAL;
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if ((unsigned long)bp_info->addr >= TASK_SIZE)
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return -EIO;
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brk.address = ALIGN_DOWN(bp_info->addr, HW_BREAKPOINT_SIZE);
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brk.type = HW_BRK_TYPE_TRANSLATE | HW_BRK_TYPE_PRIV_ALL;
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brk.len = DABR_MAX_LEN;
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brk.hw_len = DABR_MAX_LEN;
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if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
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brk.type |= HW_BRK_TYPE_READ;
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if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
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brk.type |= HW_BRK_TYPE_WRITE;
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE)
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len = bp_info->addr2 - bp_info->addr;
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else if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT)
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len = 1;
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else
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return -EINVAL;
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i = find_empty_ptrace_bp(thread);
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if (i < 0)
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return -ENOSPC;
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/* Create a new breakpoint request if one doesn't exist already */
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hw_breakpoint_init(&attr);
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attr.bp_addr = (unsigned long)bp_info->addr;
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attr.bp_len = len;
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arch_bp_generic_fields(brk.type, &attr.bp_type);
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bp = register_user_hw_breakpoint(&attr, ptrace_triggered, NULL, child);
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thread->ptrace_bps[i] = bp;
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if (IS_ERR(bp)) {
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thread->ptrace_bps[i] = NULL;
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return PTR_ERR(bp);
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}
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return i + 1;
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#endif /* CONFIG_HAVE_HW_BREAKPOINT */
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if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT)
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return -EINVAL;
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i = find_empty_hw_brk(&child->thread);
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if (i < 0)
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return -ENOSPC;
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if (!ppc_breakpoint_available())
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return -ENODEV;
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child->thread.hw_brk[i] = brk;
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return i + 1;
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}
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long ppc_del_hwdebug(struct task_struct *child, long data)
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{
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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int ret = 0;
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struct thread_struct *thread = &child->thread;
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struct perf_event *bp;
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#endif /* CONFIG_HAVE_HW_BREAKPOINT */
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if (data < 1 || data > nr_wp_slots())
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return -EINVAL;
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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bp = thread->ptrace_bps[data - 1];
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if (bp) {
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unregister_hw_breakpoint(bp);
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thread->ptrace_bps[data - 1] = NULL;
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} else {
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ret = -ENOENT;
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}
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return ret;
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#else /* CONFIG_HAVE_HW_BREAKPOINT */
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if (!(child->thread.hw_brk[data - 1].flags & HW_BRK_FLAG_DISABLED) &&
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child->thread.hw_brk[data - 1].address == 0)
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return -ENOENT;
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child->thread.hw_brk[data - 1].address = 0;
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child->thread.hw_brk[data - 1].type = 0;
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child->thread.hw_brk[data - 1].flags = 0;
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#endif /* CONFIG_HAVE_HW_BREAKPOINT */
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return 0;
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}
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