498 lines
14 KiB
C
498 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_POWERPC_MPIC_H
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#define _ASM_POWERPC_MPIC_H
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#ifdef __KERNEL__
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#include <linux/irq.h>
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#include <asm/dcr.h>
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#include <asm/msi_bitmap.h>
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/*
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* Global registers
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*/
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#define MPIC_GREG_BASE 0x01000
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#define MPIC_GREG_FEATURE_0 0x00000
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#define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
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#define MPIC_GREG_FEATURE_LAST_SRC_SHIFT 16
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#define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
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#define MPIC_GREG_FEATURE_LAST_CPU_SHIFT 8
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#define MPIC_GREG_FEATURE_VERSION_MASK 0xff
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#define MPIC_GREG_FEATURE_1 0x00010
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#define MPIC_GREG_GLOBAL_CONF_0 0x00020
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#define MPIC_GREG_GCONF_RESET 0x80000000
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/* On the FSL mpic implementations the Mode field is expand to be
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* 2 bits wide:
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* 0b00 = pass through (interrupts routed to IRQ0)
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* 0b01 = Mixed mode
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* 0b10 = reserved
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* 0b11 = External proxy / coreint
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*/
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#define MPIC_GREG_GCONF_COREINT 0x60000000
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#define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000
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#define MPIC_GREG_GCONF_NO_BIAS 0x10000000
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#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff
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#define MPIC_GREG_GCONF_MCK 0x08000000
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#define MPIC_GREG_GLOBAL_CONF_1 0x00030
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#define MPIC_GREG_VENDOR_0 0x00040
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#define MPIC_GREG_VENDOR_1 0x00050
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#define MPIC_GREG_VENDOR_2 0x00060
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#define MPIC_GREG_VENDOR_3 0x00070
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#define MPIC_GREG_VENDOR_ID 0x00080
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#define MPIC_GREG_VENDOR_ID_STEPPING_MASK 0x00ff0000
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#define MPIC_GREG_VENDOR_ID_STEPPING_SHIFT 16
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#define MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00
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#define MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT 8
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#define MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK 0x000000ff
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#define MPIC_GREG_PROCESSOR_INIT 0x00090
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#define MPIC_GREG_IPI_VECTOR_PRI_0 0x000a0
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#define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0
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#define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0
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#define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0
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#define MPIC_GREG_IPI_STRIDE 0x10
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#define MPIC_GREG_SPURIOUS 0x000e0
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#define MPIC_GREG_TIMER_FREQ 0x000f0
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/*
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*
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* Timer registers
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*/
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#define MPIC_TIMER_BASE 0x01100
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#define MPIC_TIMER_STRIDE 0x40
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#define MPIC_TIMER_GROUP_STRIDE 0x1000
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#define MPIC_TIMER_CURRENT_CNT 0x00000
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#define MPIC_TIMER_BASE_CNT 0x00010
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#define MPIC_TIMER_VECTOR_PRI 0x00020
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#define MPIC_TIMER_DESTINATION 0x00030
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/*
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* Per-Processor registers
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*/
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#define MPIC_CPU_THISBASE 0x00000
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#define MPIC_CPU_BASE 0x20000
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#define MPIC_CPU_STRIDE 0x01000
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#define MPIC_CPU_IPI_DISPATCH_0 0x00040
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#define MPIC_CPU_IPI_DISPATCH_1 0x00050
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#define MPIC_CPU_IPI_DISPATCH_2 0x00060
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#define MPIC_CPU_IPI_DISPATCH_3 0x00070
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#define MPIC_CPU_IPI_DISPATCH_STRIDE 0x00010
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#define MPIC_CPU_CURRENT_TASK_PRI 0x00080
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#define MPIC_CPU_TASKPRI_MASK 0x0000000f
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#define MPIC_CPU_WHOAMI 0x00090
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#define MPIC_CPU_WHOAMI_MASK 0x0000001f
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#define MPIC_CPU_INTACK 0x000a0
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#define MPIC_CPU_EOI 0x000b0
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#define MPIC_CPU_MCACK 0x000c0
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/*
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* Per-source registers
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*/
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#define MPIC_IRQ_BASE 0x10000
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#define MPIC_IRQ_STRIDE 0x00020
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#define MPIC_IRQ_VECTOR_PRI 0x00000
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#define MPIC_VECPRI_MASK 0x80000000
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#define MPIC_VECPRI_ACTIVITY 0x40000000 /* Read Only */
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#define MPIC_VECPRI_PRIORITY_MASK 0x000f0000
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#define MPIC_VECPRI_PRIORITY_SHIFT 16
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#define MPIC_VECPRI_VECTOR_MASK 0x000007ff
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#define MPIC_VECPRI_POLARITY_POSITIVE 0x00800000
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#define MPIC_VECPRI_POLARITY_NEGATIVE 0x00000000
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#define MPIC_VECPRI_POLARITY_MASK 0x00800000
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#define MPIC_VECPRI_SENSE_LEVEL 0x00400000
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#define MPIC_VECPRI_SENSE_EDGE 0x00000000
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#define MPIC_VECPRI_SENSE_MASK 0x00400000
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#define MPIC_IRQ_DESTINATION 0x00010
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#define MPIC_FSL_BRR1 0x00000
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#define MPIC_FSL_BRR1_VER 0x0000ffff
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#define MPIC_MAX_IRQ_SOURCES 2048
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#define MPIC_MAX_CPUS 32
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#define MPIC_MAX_ISU 32
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#define MPIC_MAX_ERR 32
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#define MPIC_FSL_ERR_INT 16
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/*
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* Tsi108 implementation of MPIC has many differences from the original one
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*/
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/*
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* Global registers
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*/
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#define TSI108_GREG_BASE 0x00000
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#define TSI108_GREG_FEATURE_0 0x00000
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#define TSI108_GREG_GLOBAL_CONF_0 0x00004
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#define TSI108_GREG_VENDOR_ID 0x0000c
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#define TSI108_GREG_IPI_VECTOR_PRI_0 0x00204 /* Doorbell 0 */
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#define TSI108_GREG_IPI_STRIDE 0x0c
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#define TSI108_GREG_SPURIOUS 0x00010
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#define TSI108_GREG_TIMER_FREQ 0x00014
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/*
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* Timer registers
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*/
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#define TSI108_TIMER_BASE 0x0030
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#define TSI108_TIMER_STRIDE 0x10
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#define TSI108_TIMER_CURRENT_CNT 0x00000
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#define TSI108_TIMER_BASE_CNT 0x00004
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#define TSI108_TIMER_VECTOR_PRI 0x00008
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#define TSI108_TIMER_DESTINATION 0x0000c
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/*
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* Per-Processor registers
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*/
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#define TSI108_CPU_BASE 0x00300
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#define TSI108_CPU_STRIDE 0x00040
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#define TSI108_CPU_IPI_DISPATCH_0 0x00200
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#define TSI108_CPU_IPI_DISPATCH_STRIDE 0x00000
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#define TSI108_CPU_CURRENT_TASK_PRI 0x00000
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#define TSI108_CPU_WHOAMI 0xffffffff
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#define TSI108_CPU_INTACK 0x00004
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#define TSI108_CPU_EOI 0x00008
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#define TSI108_CPU_MCACK 0x00004 /* Doesn't really exist here */
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/*
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* Per-source registers
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*/
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#define TSI108_IRQ_BASE 0x00100
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#define TSI108_IRQ_STRIDE 0x00008
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#define TSI108_IRQ_VECTOR_PRI 0x00000
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#define TSI108_VECPRI_VECTOR_MASK 0x000000ff
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#define TSI108_VECPRI_POLARITY_POSITIVE 0x01000000
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#define TSI108_VECPRI_POLARITY_NEGATIVE 0x00000000
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#define TSI108_VECPRI_SENSE_LEVEL 0x02000000
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#define TSI108_VECPRI_SENSE_EDGE 0x00000000
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#define TSI108_VECPRI_POLARITY_MASK 0x01000000
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#define TSI108_VECPRI_SENSE_MASK 0x02000000
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#define TSI108_IRQ_DESTINATION 0x00004
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/* weird mpic register indices and mask bits in the HW info array */
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enum {
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MPIC_IDX_GREG_BASE = 0,
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MPIC_IDX_GREG_FEATURE_0,
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MPIC_IDX_GREG_GLOBAL_CONF_0,
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MPIC_IDX_GREG_VENDOR_ID,
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MPIC_IDX_GREG_IPI_VECTOR_PRI_0,
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MPIC_IDX_GREG_IPI_STRIDE,
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MPIC_IDX_GREG_SPURIOUS,
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MPIC_IDX_GREG_TIMER_FREQ,
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MPIC_IDX_TIMER_BASE,
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MPIC_IDX_TIMER_STRIDE,
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MPIC_IDX_TIMER_CURRENT_CNT,
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MPIC_IDX_TIMER_BASE_CNT,
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MPIC_IDX_TIMER_VECTOR_PRI,
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MPIC_IDX_TIMER_DESTINATION,
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MPIC_IDX_CPU_BASE,
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MPIC_IDX_CPU_STRIDE,
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MPIC_IDX_CPU_IPI_DISPATCH_0,
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MPIC_IDX_CPU_IPI_DISPATCH_STRIDE,
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MPIC_IDX_CPU_CURRENT_TASK_PRI,
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MPIC_IDX_CPU_WHOAMI,
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MPIC_IDX_CPU_INTACK,
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MPIC_IDX_CPU_EOI,
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MPIC_IDX_CPU_MCACK,
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MPIC_IDX_IRQ_BASE,
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MPIC_IDX_IRQ_STRIDE,
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MPIC_IDX_IRQ_VECTOR_PRI,
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MPIC_IDX_VECPRI_VECTOR_MASK,
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MPIC_IDX_VECPRI_POLARITY_POSITIVE,
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MPIC_IDX_VECPRI_POLARITY_NEGATIVE,
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MPIC_IDX_VECPRI_SENSE_LEVEL,
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MPIC_IDX_VECPRI_SENSE_EDGE,
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MPIC_IDX_VECPRI_POLARITY_MASK,
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MPIC_IDX_VECPRI_SENSE_MASK,
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MPIC_IDX_IRQ_DESTINATION,
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MPIC_IDX_END
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};
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#ifdef CONFIG_MPIC_U3_HT_IRQS
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/* Fixup table entry */
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struct mpic_irq_fixup
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{
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u8 __iomem *base;
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u8 __iomem *applebase;
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u32 data;
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unsigned int index;
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};
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#endif /* CONFIG_MPIC_U3_HT_IRQS */
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enum mpic_reg_type {
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mpic_access_mmio_le,
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mpic_access_mmio_be,
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#ifdef CONFIG_PPC_DCR
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mpic_access_dcr
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#endif
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};
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struct mpic_reg_bank {
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u32 __iomem *base;
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#ifdef CONFIG_PPC_DCR
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dcr_host_t dhost;
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#endif /* CONFIG_PPC_DCR */
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};
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struct mpic_irq_save {
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u32 vecprio,
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dest;
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#ifdef CONFIG_MPIC_U3_HT_IRQS
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u32 fixup_data;
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#endif
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};
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/* The instance data of a given MPIC */
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struct mpic
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{
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/* The OpenFirmware dt node for this MPIC */
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struct device_node *node;
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/* The remapper for this MPIC */
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struct irq_domain *irqhost;
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/* The "linux" controller struct */
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struct irq_chip hc_irq;
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#ifdef CONFIG_MPIC_U3_HT_IRQS
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struct irq_chip hc_ht_irq;
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#endif
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#ifdef CONFIG_SMP
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struct irq_chip hc_ipi;
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#endif
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struct irq_chip hc_tm;
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struct irq_chip hc_err;
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const char *name;
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/* Flags */
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unsigned int flags;
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/* How many irq sources in a given ISU */
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unsigned int isu_size;
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unsigned int isu_shift;
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unsigned int isu_mask;
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/* Number of sources */
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unsigned int num_sources;
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/* vector numbers used for internal sources (ipi/timers) */
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unsigned int ipi_vecs[4];
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unsigned int timer_vecs[8];
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/* vector numbers used for FSL MPIC error interrupts */
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unsigned int err_int_vecs[MPIC_MAX_ERR];
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/* Spurious vector to program into unused sources */
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unsigned int spurious_vec;
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#ifdef CONFIG_MPIC_U3_HT_IRQS
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/* The fixup table */
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struct mpic_irq_fixup *fixups;
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raw_spinlock_t fixup_lock;
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#endif
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/* Register access method */
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enum mpic_reg_type reg_type;
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/* The physical base address of the MPIC */
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phys_addr_t paddr;
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/* The various ioremap'ed bases */
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struct mpic_reg_bank thiscpuregs;
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struct mpic_reg_bank gregs;
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struct mpic_reg_bank tmregs;
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struct mpic_reg_bank cpuregs[MPIC_MAX_CPUS];
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struct mpic_reg_bank isus[MPIC_MAX_ISU];
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/* ioremap'ed base for error interrupt registers */
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u32 __iomem *err_regs;
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/* Protected sources */
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unsigned long *protected;
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#ifdef CONFIG_MPIC_WEIRD
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/* Pointer to HW info array */
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u32 *hw_set;
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#endif
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#ifdef CONFIG_PCI_MSI
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struct msi_bitmap msi_bitmap;
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#endif
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#ifdef CONFIG_MPIC_BROKEN_REGREAD
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u32 isu_reg0_shadow[MPIC_MAX_IRQ_SOURCES];
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#endif
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/* link */
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struct mpic *next;
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#ifdef CONFIG_PM
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struct mpic_irq_save *save_data;
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#endif
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};
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extern struct bus_type mpic_subsys;
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/*
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* MPIC flags (passed to mpic_alloc)
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*
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* The top 4 bits contain an MPIC bhw id that is used to index the
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* register offsets and some masks when CONFIG_MPIC_WEIRD is set.
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* Note setting any ID (leaving those bits to 0) means standard MPIC
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*/
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/*
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* This is a secondary ("chained") controller; it only uses the CPU0
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* registers. Primary controllers have IPIs and affinity control.
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*/
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#define MPIC_SECONDARY 0x00000001
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/* Set this for a big-endian MPIC */
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#define MPIC_BIG_ENDIAN 0x00000002
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/* Broken U3 MPIC */
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#define MPIC_U3_HT_IRQS 0x00000004
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/* Broken IPI registers (autodetected) */
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#define MPIC_BROKEN_IPI 0x00000008
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/* Spurious vector requires EOI */
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#define MPIC_SPV_EOI 0x00000020
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/* No passthrough disable */
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#define MPIC_NO_PTHROU_DIS 0x00000040
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/* DCR based MPIC */
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#define MPIC_USES_DCR 0x00000080
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/* MPIC has 11-bit vector fields (or larger) */
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#define MPIC_LARGE_VECTORS 0x00000100
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/* Enable delivery of prio 15 interrupts as MCK instead of EE */
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#define MPIC_ENABLE_MCK 0x00000200
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/* Disable bias among target selection, spread interrupts evenly */
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#define MPIC_NO_BIAS 0x00000400
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/* Destination only supports a single CPU at a time */
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#define MPIC_SINGLE_DEST_CPU 0x00001000
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/* Enable CoreInt delivery of interrupts */
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#define MPIC_ENABLE_COREINT 0x00002000
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/* Do not reset the MPIC during initialization */
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#define MPIC_NO_RESET 0x00004000
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/* Freescale MPIC (compatible includes "fsl,mpic") */
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#define MPIC_FSL 0x00008000
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/* Freescale MPIC supports EIMR (error interrupt mask register).
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* This flag is set for MPIC version >= 4.1 (version determined
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* from the BRR1 register).
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*/
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#define MPIC_FSL_HAS_EIMR 0x00010000
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/* MPIC HW modification ID */
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#define MPIC_REGSET_MASK 0xf0000000
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#define MPIC_REGSET(val) (((val) & 0xf ) << 28)
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#define MPIC_GET_REGSET(flags) (((flags) >> 28) & 0xf)
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#define MPIC_REGSET_STANDARD MPIC_REGSET(0) /* Original MPIC */
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#define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109 PIC */
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/* Get the version of primary MPIC */
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#ifdef CONFIG_MPIC
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extern u32 fsl_mpic_primary_get_version(void);
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#else
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static inline u32 fsl_mpic_primary_get_version(void)
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{
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return 0;
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}
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#endif
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/* Allocate the controller structure and setup the linux irq descs
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* for the range if interrupts passed in. No HW initialization is
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* actually performed.
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*
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* @phys_addr: physial base address of the MPIC
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* @flags: flags, see constants above
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* @isu_size: number of interrupts in an ISU. Use 0 to use a
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* standard ISU-less setup (aka powermac)
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* @irq_offset: first irq number to assign to this mpic
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* @irq_count: number of irqs to use with this mpic IRQ sources. Pass 0
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* to match the number of sources
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* @ipi_offset: first irq number to assign to this mpic IPI sources,
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* used only on primary mpic
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* @senses: array of sense values
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* @senses_num: number of entries in the array
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*
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* Note about the sense array. If none is passed, all interrupts are
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* setup to be level negative unless MPIC_U3_HT_IRQS is set in which
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* case they are edge positive (and the array is ignored anyway).
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* The values in the array start at the first source of the MPIC,
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* that is senses[0] correspond to linux irq "irq_offset".
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*/
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extern struct mpic *mpic_alloc(struct device_node *node,
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phys_addr_t phys_addr,
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unsigned int flags,
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unsigned int isu_size,
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unsigned int irq_count,
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const char *name);
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/* Assign ISUs, to call before mpic_init()
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*
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* @mpic: controller structure as returned by mpic_alloc()
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* @isu_num: ISU number
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* @phys_addr: physical address of the ISU
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*/
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extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
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phys_addr_t phys_addr);
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/* Initialize the controller. After this has been called, none of the above
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* should be called again for this mpic
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*/
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extern void mpic_init(struct mpic *mpic);
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/*
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* All of the following functions must only be used after the
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* ISUs have been assigned and the controller fully initialized
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* with mpic_init()
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*/
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/* Change the priority of an interrupt. Default is 8 for irqs and
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* 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
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* IPI number is then the offset'ed (linux irq number mapped to the IPI)
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*/
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extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
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/* Setup a non-boot CPU */
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extern void mpic_setup_this_cpu(void);
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/* Clean up for kexec (or cpu offline or ...) */
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extern void mpic_teardown_this_cpu(int secondary);
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/* Get the current cpu priority for this cpu (0..15) */
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extern int mpic_cpu_get_priority(void);
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/* Set the current cpu priority for this cpu */
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extern void mpic_cpu_set_priority(int prio);
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/* Request IPIs on primary mpic */
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void __init mpic_request_ipis(void);
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/* Send a message (IPI) to a given target (cpu number or MSG_*) */
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void smp_mpic_message_pass(int target, int msg);
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/* Unmask a specific virq */
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extern void mpic_unmask_irq(struct irq_data *d);
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/* Mask a specific virq */
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extern void mpic_mask_irq(struct irq_data *d);
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/* EOI a specific virq */
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extern void mpic_end_irq(struct irq_data *d);
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/* Fetch interrupt from a given mpic */
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extern unsigned int mpic_get_one_irq(struct mpic *mpic);
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/* This one gets from the primary mpic */
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extern unsigned int mpic_get_irq(void);
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/* This one gets from the primary mpic via CoreInt*/
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extern unsigned int mpic_get_coreint_irq(void);
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/* Fetch Machine Check interrupt from primary mpic */
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extern unsigned int mpic_get_mcirq(void);
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_MPIC_H */
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