143 lines
3.2 KiB
Plaintext
143 lines
3.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Freescale Media5200 board Device Tree Source
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*
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* Copyright 2009 Secret Lab Technologies Ltd.
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* Grant Likely <grant.likely@secretlab.ca>
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* Steven Cavanagh <scavanagh@secretlab.ca>
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*/
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/include/ "mpc5200b.dtsi"
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&gpt0 { fsl,has-wdt; };
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/ {
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model = "fsl,media5200";
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compatible = "fsl,media5200";
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aliases {
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console = &console;
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ethernet0 = ð0;
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};
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chosen {
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stdout-path = &console;
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};
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cpus {
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PowerPC,5200@0 {
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timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
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bus-frequency = <132000000>; // 132 MHz
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clock-frequency = <396000000>; // 396 MHz
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};
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};
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memory@0 {
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reg = <0x00000000 0x08000000>; // 128MB RAM
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};
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soc5200@f0000000 {
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bus-frequency = <132000000>;// 132 MHz
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psc@2000 { // PSC1
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status = "disabled";
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};
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psc@2200 { // PSC2
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status = "disabled";
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};
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psc@2400 { // PSC3
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status = "disabled";
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};
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psc@2600 { // PSC4
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status = "disabled";
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};
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psc@2800 { // PSC5
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status = "disabled";
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};
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// PSC6 in uart mode
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console: psc@2c00 { // PSC6
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compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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};
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ethernet@3000 {
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phy-handle = <&phy0>;
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};
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mdio@3000 {
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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usb@1000 {
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reg = <0x1000 0x100>;
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};
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};
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pci@f0000d00 {
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot
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0xc000 0 0 2 &media5200_fpga 0 3
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0xc000 0 0 3 &media5200_fpga 0 4
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0xc000 0 0 4 &media5200_fpga 0 5
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0xc800 0 0 1 &media5200_fpga 0 3 // 2nd slot
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0xc800 0 0 2 &media5200_fpga 0 4
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0xc800 0 0 3 &media5200_fpga 0 5
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0xc800 0 0 4 &media5200_fpga 0 2
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0xd000 0 0 1 &media5200_fpga 0 4 // miniPCI
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0xd000 0 0 2 &media5200_fpga 0 5
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0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP
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>;
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ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000>,
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<0x02000000 0 0xa0000000 0xa0000000 0 0x10000000>,
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<0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
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interrupt-parent = <&mpc5200_pic>;
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};
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localbus {
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ranges = < 0 0 0xfc000000 0x02000000
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1 0 0xfe000000 0x02000000
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2 0 0xf0010000 0x00010000
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3 0 0xf0020000 0x00010000 >;
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flash@0,0 {
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compatible = "amd,am29lv28ml", "cfi-flash";
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reg = <0 0x0 0x2000000>; // 32 MB
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bank-width = <4>; // Width in bytes of the flash bank
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device-width = <2>; // Two devices on each bank
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};
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flash@1,0 {
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compatible = "amd,am29lv28ml", "cfi-flash";
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reg = <1 0 0x2000000>; // 32 MB
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bank-width = <4>; // Width in bytes of the flash bank
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device-width = <2>; // Two devices on each bank
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};
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media5200_fpga: fpga@2,0 {
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compatible = "fsl,media5200-fpga";
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interrupt-controller;
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#interrupt-cells = <2>; // 0:bank 1:id; no type field
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reg = <2 0 0x10000>;
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interrupt-parent = <&mpc5200_pic>;
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interrupts = <0 0 3 // IRQ bank 0
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1 1 3>; // IRQ bank 1
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};
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uart@3,0 {
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compatible = "ti,tl16c752bpt";
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reg = <3 0 0x10000>;
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interrupt-parent = <&media5200_fpga>;
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interrupts = <0 0 0 1>; // 2 irqs
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};
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};
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};
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