427 lines
11 KiB
C
427 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* Derived from arch/arm/kvm/reset.c
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*/
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/kvm_host.h>
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#include <linux/kvm.h>
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#include <linux/hw_breakpoint.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <kvm/arm_arch_timer.h>
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#include <asm/cpufeature.h>
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#include <asm/cputype.h>
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#include <asm/fpsimd.h>
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#include <asm/ptrace.h>
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#include <asm/kvm_arm.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_mmu.h>
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#include <asm/virt.h>
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/* Maximum phys_shift supported for any VM on this host */
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static u32 kvm_ipa_limit;
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/*
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* ARMv8 Reset Values
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*/
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#define VCPU_RESET_PSTATE_EL1 (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT | \
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PSR_F_BIT | PSR_D_BIT)
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#define VCPU_RESET_PSTATE_SVC (PSR_AA32_MODE_SVC | PSR_AA32_A_BIT | \
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PSR_AA32_I_BIT | PSR_AA32_F_BIT)
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unsigned int kvm_sve_max_vl;
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int kvm_arm_init_sve(void)
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{
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if (system_supports_sve()) {
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kvm_sve_max_vl = sve_max_virtualisable_vl();
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/*
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* The get_sve_reg()/set_sve_reg() ioctl interface will need
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* to be extended with multiple register slice support in
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* order to support vector lengths greater than
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* VL_ARCH_MAX:
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*/
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if (WARN_ON(kvm_sve_max_vl > VL_ARCH_MAX))
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kvm_sve_max_vl = VL_ARCH_MAX;
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/*
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* Don't even try to make use of vector lengths that
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* aren't available on all CPUs, for now:
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*/
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if (kvm_sve_max_vl < sve_max_vl())
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pr_warn("KVM: SVE vector length for guests limited to %u bytes\n",
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kvm_sve_max_vl);
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}
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return 0;
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}
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static int kvm_vcpu_enable_sve(struct kvm_vcpu *vcpu)
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{
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if (!system_supports_sve())
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return -EINVAL;
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vcpu->arch.sve_max_vl = kvm_sve_max_vl;
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/*
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* Userspace can still customize the vector lengths by writing
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* KVM_REG_ARM64_SVE_VLS. Allocation is deferred until
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* kvm_arm_vcpu_finalize(), which freezes the configuration.
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*/
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vcpu->arch.flags |= KVM_ARM64_GUEST_HAS_SVE;
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return 0;
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}
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/*
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* Finalize vcpu's maximum SVE vector length, allocating
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* vcpu->arch.sve_state as necessary.
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*/
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static int kvm_vcpu_finalize_sve(struct kvm_vcpu *vcpu)
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{
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void *buf;
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unsigned int vl;
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size_t reg_sz;
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int ret;
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vl = vcpu->arch.sve_max_vl;
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/*
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* Responsibility for these properties is shared between
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* kvm_arm_init_sve(), kvm_vcpu_enable_sve() and
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* set_sve_vls(). Double-check here just to be sure:
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*/
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if (WARN_ON(!sve_vl_valid(vl) || vl > sve_max_virtualisable_vl() ||
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vl > VL_ARCH_MAX))
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return -EIO;
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reg_sz = vcpu_sve_state_size(vcpu);
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buf = kzalloc(reg_sz, GFP_KERNEL_ACCOUNT);
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if (!buf)
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return -ENOMEM;
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ret = kvm_share_hyp(buf, buf + reg_sz);
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if (ret) {
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kfree(buf);
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return ret;
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}
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vcpu->arch.sve_state = buf;
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vcpu->arch.flags |= KVM_ARM64_VCPU_SVE_FINALIZED;
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return 0;
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}
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int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature)
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{
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switch (feature) {
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case KVM_ARM_VCPU_SVE:
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if (!vcpu_has_sve(vcpu))
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return -EINVAL;
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if (kvm_arm_vcpu_sve_finalized(vcpu))
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return -EPERM;
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return kvm_vcpu_finalize_sve(vcpu);
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}
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return -EINVAL;
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}
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bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu)
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{
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if (vcpu_has_sve(vcpu) && !kvm_arm_vcpu_sve_finalized(vcpu))
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return false;
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return true;
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}
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void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu)
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{
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void *sve_state = vcpu->arch.sve_state;
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kvm_vcpu_unshare_task_fp(vcpu);
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kvm_unshare_hyp(vcpu, vcpu + 1);
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if (sve_state)
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kvm_unshare_hyp(sve_state, sve_state + vcpu_sve_state_size(vcpu));
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kfree(sve_state);
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}
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static void kvm_vcpu_reset_sve(struct kvm_vcpu *vcpu)
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{
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if (vcpu_has_sve(vcpu))
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memset(vcpu->arch.sve_state, 0, vcpu_sve_state_size(vcpu));
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}
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static int kvm_vcpu_enable_ptrauth(struct kvm_vcpu *vcpu)
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{
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/*
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* For now make sure that both address/generic pointer authentication
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* features are requested by the userspace together and the system
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* supports these capabilities.
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*/
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if (!test_bit(KVM_ARM_VCPU_PTRAUTH_ADDRESS, vcpu->arch.features) ||
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!test_bit(KVM_ARM_VCPU_PTRAUTH_GENERIC, vcpu->arch.features) ||
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!system_has_full_ptr_auth())
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return -EINVAL;
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vcpu->arch.flags |= KVM_ARM64_GUEST_HAS_PTRAUTH;
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return 0;
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}
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/**
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* kvm_set_vm_width() - set the register width for the guest
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* @vcpu: Pointer to the vcpu being configured
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*
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* Set both KVM_ARCH_FLAG_EL1_32BIT and KVM_ARCH_FLAG_REG_WIDTH_CONFIGURED
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* in the VM flags based on the vcpu's requested register width, the HW
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* capabilities and other options (such as MTE).
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* When REG_WIDTH_CONFIGURED is already set, the vcpu settings must be
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* consistent with the value of the FLAG_EL1_32BIT bit in the flags.
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*
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* Return: 0 on success, negative error code on failure.
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*/
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static int kvm_set_vm_width(struct kvm_vcpu *vcpu)
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{
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struct kvm *kvm = vcpu->kvm;
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bool is32bit;
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is32bit = vcpu_has_feature(vcpu, KVM_ARM_VCPU_EL1_32BIT);
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lockdep_assert_held(&kvm->lock);
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if (test_bit(KVM_ARCH_FLAG_REG_WIDTH_CONFIGURED, &kvm->arch.flags)) {
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/*
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* The guest's register width is already configured.
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* Make sure that the vcpu is consistent with it.
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*/
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if (is32bit == test_bit(KVM_ARCH_FLAG_EL1_32BIT, &kvm->arch.flags))
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return 0;
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return -EINVAL;
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}
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if (!cpus_have_const_cap(ARM64_HAS_32BIT_EL1) && is32bit)
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return -EINVAL;
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/* MTE is incompatible with AArch32 */
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if (kvm_has_mte(kvm) && is32bit)
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return -EINVAL;
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if (is32bit)
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set_bit(KVM_ARCH_FLAG_EL1_32BIT, &kvm->arch.flags);
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set_bit(KVM_ARCH_FLAG_REG_WIDTH_CONFIGURED, &kvm->arch.flags);
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return 0;
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}
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/**
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* kvm_reset_vcpu - sets core registers and sys_regs to reset value
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* @vcpu: The VCPU pointer
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*
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* This function sets the registers on the virtual CPU struct to their
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* architecturally defined reset values, except for registers whose reset is
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* deferred until kvm_arm_vcpu_finalize().
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*
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* Note: This function can be called from two paths: The KVM_ARM_VCPU_INIT
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* ioctl or as part of handling a request issued by another VCPU in the PSCI
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* handling code. In the first case, the VCPU will not be loaded, and in the
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* second case the VCPU will be loaded. Because this function operates purely
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* on the memory-backed values of system registers, we want to do a full put if
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* we were loaded (handling a request) and load the values back at the end of
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* the function. Otherwise we leave the state alone. In both cases, we
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* disable preemption around the vcpu reset as we would otherwise race with
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* preempt notifiers which also call put/load.
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*/
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int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
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{
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struct vcpu_reset_state reset_state;
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int ret;
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bool loaded;
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u32 pstate;
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mutex_lock(&vcpu->kvm->lock);
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ret = kvm_set_vm_width(vcpu);
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if (!ret) {
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reset_state = vcpu->arch.reset_state;
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WRITE_ONCE(vcpu->arch.reset_state.reset, false);
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}
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mutex_unlock(&vcpu->kvm->lock);
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if (ret)
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return ret;
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/* Reset PMU outside of the non-preemptible section */
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kvm_pmu_vcpu_reset(vcpu);
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preempt_disable();
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loaded = (vcpu->cpu != -1);
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if (loaded)
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kvm_arch_vcpu_put(vcpu);
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if (!kvm_arm_vcpu_sve_finalized(vcpu)) {
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if (test_bit(KVM_ARM_VCPU_SVE, vcpu->arch.features)) {
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ret = kvm_vcpu_enable_sve(vcpu);
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if (ret)
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goto out;
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}
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} else {
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kvm_vcpu_reset_sve(vcpu);
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}
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if (test_bit(KVM_ARM_VCPU_PTRAUTH_ADDRESS, vcpu->arch.features) ||
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test_bit(KVM_ARM_VCPU_PTRAUTH_GENERIC, vcpu->arch.features)) {
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if (kvm_vcpu_enable_ptrauth(vcpu)) {
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ret = -EINVAL;
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goto out;
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}
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}
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switch (vcpu->arch.target) {
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default:
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if (vcpu_el1_is_32bit(vcpu)) {
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pstate = VCPU_RESET_PSTATE_SVC;
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} else {
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pstate = VCPU_RESET_PSTATE_EL1;
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}
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if (kvm_vcpu_has_pmu(vcpu) && !kvm_arm_support_pmu_v3()) {
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ret = -EINVAL;
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goto out;
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}
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break;
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}
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/* Reset core registers */
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memset(vcpu_gp_regs(vcpu), 0, sizeof(*vcpu_gp_regs(vcpu)));
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memset(&vcpu->arch.ctxt.fp_regs, 0, sizeof(vcpu->arch.ctxt.fp_regs));
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vcpu->arch.ctxt.spsr_abt = 0;
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vcpu->arch.ctxt.spsr_und = 0;
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vcpu->arch.ctxt.spsr_irq = 0;
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vcpu->arch.ctxt.spsr_fiq = 0;
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vcpu_gp_regs(vcpu)->pstate = pstate;
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/* Reset system registers */
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kvm_reset_sys_regs(vcpu);
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/*
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* Additional reset state handling that PSCI may have imposed on us.
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* Must be done after all the sys_reg reset.
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*/
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if (reset_state.reset) {
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unsigned long target_pc = reset_state.pc;
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/* Gracefully handle Thumb2 entry point */
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if (vcpu_mode_is_32bit(vcpu) && (target_pc & 1)) {
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target_pc &= ~1UL;
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vcpu_set_thumb(vcpu);
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}
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/* Propagate caller endianness */
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if (reset_state.be)
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kvm_vcpu_set_be(vcpu);
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*vcpu_pc(vcpu) = target_pc;
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vcpu_set_reg(vcpu, 0, reset_state.r0);
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}
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/* Reset timer */
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ret = kvm_timer_vcpu_reset(vcpu);
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out:
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if (loaded)
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kvm_arch_vcpu_load(vcpu, smp_processor_id());
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preempt_enable();
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return ret;
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}
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u32 get_kvm_ipa_limit(void)
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{
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return kvm_ipa_limit;
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}
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int kvm_set_ipa_limit(void)
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{
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unsigned int parange;
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u64 mmfr0;
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mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
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parange = cpuid_feature_extract_unsigned_field(mmfr0,
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ID_AA64MMFR0_PARANGE_SHIFT);
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/*
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* IPA size beyond 48 bits could not be supported
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* on either 4K or 16K page size. Hence let's cap
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* it to 48 bits, in case it's reported as larger
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* on the system.
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*/
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if (PAGE_SIZE != SZ_64K)
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parange = min(parange, (unsigned int)ID_AA64MMFR0_PARANGE_48);
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/*
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* Check with ARMv8.5-GTG that our PAGE_SIZE is supported at
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* Stage-2. If not, things will stop very quickly.
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*/
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switch (cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_TGRAN_2_SHIFT)) {
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case ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE:
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kvm_err("PAGE_SIZE not supported at Stage-2, giving up\n");
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return -EINVAL;
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case ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT:
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kvm_debug("PAGE_SIZE supported at Stage-2 (default)\n");
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break;
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case ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN ... ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX:
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kvm_debug("PAGE_SIZE supported at Stage-2 (advertised)\n");
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break;
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default:
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kvm_err("Unsupported value for TGRAN_2, giving up\n");
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return -EINVAL;
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}
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kvm_ipa_limit = id_aa64mmfr0_parange_to_phys_shift(parange);
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kvm_info("IPA Size Limit: %d bits%s\n", kvm_ipa_limit,
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((kvm_ipa_limit < KVM_PHYS_SHIFT) ?
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" (Reduced IPA size, limited VM/VMM compatibility)" : ""));
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return 0;
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}
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int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type)
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{
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u64 mmfr0, mmfr1;
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u32 phys_shift;
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if (type & ~KVM_VM_TYPE_ARM_IPA_SIZE_MASK)
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return -EINVAL;
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phys_shift = KVM_VM_TYPE_ARM_IPA_SIZE(type);
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if (phys_shift) {
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if (phys_shift > kvm_ipa_limit ||
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phys_shift < ARM64_MIN_PARANGE_BITS)
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return -EINVAL;
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} else {
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phys_shift = KVM_PHYS_SHIFT;
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if (phys_shift > kvm_ipa_limit) {
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pr_warn_once("%s using unsupported default IPA limit, upgrade your VMM\n",
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current->comm);
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return -EINVAL;
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}
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}
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mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
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mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
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kvm->arch.vtcr = kvm_get_vtcr(mmfr0, mmfr1, phys_shift);
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return 0;
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}
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