352 lines
9.7 KiB
C
352 lines
9.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Fault injection for both 32 and 64bit guests.
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*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* Based on arch/arm/kvm/emulate.c
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*/
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#include <hyp/adjust_pc.h>
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#include <linux/kvm_host.h>
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#include <asm/kvm_emulate.h>
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#if !defined (__KVM_NVHE_HYPERVISOR__) && !defined (__KVM_VHE_HYPERVISOR__)
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#error Hypervisor code only!
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#endif
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static inline u64 __vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
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{
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u64 val;
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if (__vcpu_read_sys_reg_from_cpu(reg, &val))
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return val;
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return __vcpu_sys_reg(vcpu, reg);
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}
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static inline void __vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
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{
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if (__vcpu_write_sys_reg_to_cpu(val, reg))
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return;
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__vcpu_sys_reg(vcpu, reg) = val;
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}
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static void __vcpu_write_spsr(struct kvm_vcpu *vcpu, u64 val)
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{
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if (has_vhe())
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write_sysreg_el1(val, SYS_SPSR);
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else
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__vcpu_sys_reg(vcpu, SPSR_EL1) = val;
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}
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static void __vcpu_write_spsr_abt(struct kvm_vcpu *vcpu, u64 val)
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{
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if (has_vhe())
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write_sysreg(val, spsr_abt);
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else
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vcpu->arch.ctxt.spsr_abt = val;
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}
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static void __vcpu_write_spsr_und(struct kvm_vcpu *vcpu, u64 val)
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{
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if (has_vhe())
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write_sysreg(val, spsr_und);
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else
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vcpu->arch.ctxt.spsr_und = val;
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}
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/*
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* This performs the exception entry at a given EL (@target_mode), stashing PC
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* and PSTATE into ELR and SPSR respectively, and compute the new PC/PSTATE.
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* The EL passed to this function *must* be a non-secure, privileged mode with
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* bit 0 being set (PSTATE.SP == 1).
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*
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* When an exception is taken, most PSTATE fields are left unchanged in the
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* handler. However, some are explicitly overridden (e.g. M[4:0]). Luckily all
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* of the inherited bits have the same position in the AArch64/AArch32 SPSR_ELx
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* layouts, so we don't need to shuffle these for exceptions from AArch32 EL0.
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*
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* For the SPSR_ELx layout for AArch64, see ARM DDI 0487E.a page C5-429.
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* For the SPSR_ELx layout for AArch32, see ARM DDI 0487E.a page C5-426.
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*
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* Here we manipulate the fields in order of the AArch64 SPSR_ELx layout, from
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* MSB to LSB.
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*/
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static void enter_exception64(struct kvm_vcpu *vcpu, unsigned long target_mode,
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enum exception_type type)
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{
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unsigned long sctlr, vbar, old, new, mode;
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u64 exc_offset;
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mode = *vcpu_cpsr(vcpu) & (PSR_MODE_MASK | PSR_MODE32_BIT);
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if (mode == target_mode)
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exc_offset = CURRENT_EL_SP_ELx_VECTOR;
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else if ((mode | PSR_MODE_THREAD_BIT) == target_mode)
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exc_offset = CURRENT_EL_SP_EL0_VECTOR;
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else if (!(mode & PSR_MODE32_BIT))
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exc_offset = LOWER_EL_AArch64_VECTOR;
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else
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exc_offset = LOWER_EL_AArch32_VECTOR;
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switch (target_mode) {
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case PSR_MODE_EL1h:
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vbar = __vcpu_read_sys_reg(vcpu, VBAR_EL1);
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sctlr = __vcpu_read_sys_reg(vcpu, SCTLR_EL1);
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__vcpu_write_sys_reg(vcpu, *vcpu_pc(vcpu), ELR_EL1);
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break;
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default:
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/* Don't do that */
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BUG();
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}
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*vcpu_pc(vcpu) = vbar + exc_offset + type;
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old = *vcpu_cpsr(vcpu);
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new = 0;
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new |= (old & PSR_N_BIT);
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new |= (old & PSR_Z_BIT);
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new |= (old & PSR_C_BIT);
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new |= (old & PSR_V_BIT);
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if (kvm_has_mte(vcpu->kvm))
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new |= PSR_TCO_BIT;
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new |= (old & PSR_DIT_BIT);
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// PSTATE.UAO is set to zero upon any exception to AArch64
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// See ARM DDI 0487E.a, page D5-2579.
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// PSTATE.PAN is unchanged unless SCTLR_ELx.SPAN == 0b0
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// SCTLR_ELx.SPAN is RES1 when ARMv8.1-PAN is not implemented
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// See ARM DDI 0487E.a, page D5-2578.
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new |= (old & PSR_PAN_BIT);
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if (!(sctlr & SCTLR_EL1_SPAN))
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new |= PSR_PAN_BIT;
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// PSTATE.SS is set to zero upon any exception to AArch64
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// See ARM DDI 0487E.a, page D2-2452.
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// PSTATE.IL is set to zero upon any exception to AArch64
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// See ARM DDI 0487E.a, page D1-2306.
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// PSTATE.SSBS is set to SCTLR_ELx.DSSBS upon any exception to AArch64
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// See ARM DDI 0487E.a, page D13-3258
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if (sctlr & SCTLR_ELx_DSSBS)
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new |= PSR_SSBS_BIT;
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// PSTATE.BTYPE is set to zero upon any exception to AArch64
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// See ARM DDI 0487E.a, pages D1-2293 to D1-2294.
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new |= PSR_D_BIT;
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new |= PSR_A_BIT;
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new |= PSR_I_BIT;
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new |= PSR_F_BIT;
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new |= target_mode;
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*vcpu_cpsr(vcpu) = new;
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__vcpu_write_spsr(vcpu, old);
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}
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/*
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* When an exception is taken, most CPSR fields are left unchanged in the
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* handler. However, some are explicitly overridden (e.g. M[4:0]).
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*
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* The SPSR/SPSR_ELx layouts differ, and the below is intended to work with
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* either format. Note: SPSR.J bit doesn't exist in SPSR_ELx, but this bit was
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* obsoleted by the ARMv7 virtualization extensions and is RES0.
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*
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* For the SPSR layout seen from AArch32, see:
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* - ARM DDI 0406C.d, page B1-1148
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* - ARM DDI 0487E.a, page G8-6264
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*
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* For the SPSR_ELx layout for AArch32 seen from AArch64, see:
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* - ARM DDI 0487E.a, page C5-426
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*
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* Here we manipulate the fields in order of the AArch32 SPSR_ELx layout, from
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* MSB to LSB.
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*/
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static unsigned long get_except32_cpsr(struct kvm_vcpu *vcpu, u32 mode)
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{
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u32 sctlr = __vcpu_read_sys_reg(vcpu, SCTLR_EL1);
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unsigned long old, new;
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old = *vcpu_cpsr(vcpu);
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new = 0;
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new |= (old & PSR_AA32_N_BIT);
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new |= (old & PSR_AA32_Z_BIT);
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new |= (old & PSR_AA32_C_BIT);
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new |= (old & PSR_AA32_V_BIT);
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new |= (old & PSR_AA32_Q_BIT);
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// CPSR.IT[7:0] are set to zero upon any exception
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// See ARM DDI 0487E.a, section G1.12.3
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// See ARM DDI 0406C.d, section B1.8.3
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new |= (old & PSR_AA32_DIT_BIT);
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// CPSR.SSBS is set to SCTLR.DSSBS upon any exception
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// See ARM DDI 0487E.a, page G8-6244
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if (sctlr & BIT(31))
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new |= PSR_AA32_SSBS_BIT;
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// CPSR.PAN is unchanged unless SCTLR.SPAN == 0b0
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// SCTLR.SPAN is RES1 when ARMv8.1-PAN is not implemented
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// See ARM DDI 0487E.a, page G8-6246
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new |= (old & PSR_AA32_PAN_BIT);
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if (!(sctlr & BIT(23)))
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new |= PSR_AA32_PAN_BIT;
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// SS does not exist in AArch32, so ignore
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// CPSR.IL is set to zero upon any exception
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// See ARM DDI 0487E.a, page G1-5527
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new |= (old & PSR_AA32_GE_MASK);
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// CPSR.IT[7:0] are set to zero upon any exception
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// See prior comment above
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// CPSR.E is set to SCTLR.EE upon any exception
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// See ARM DDI 0487E.a, page G8-6245
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// See ARM DDI 0406C.d, page B4-1701
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if (sctlr & BIT(25))
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new |= PSR_AA32_E_BIT;
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// CPSR.A is unchanged upon an exception to Undefined, Supervisor
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// CPSR.A is set upon an exception to other modes
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// See ARM DDI 0487E.a, pages G1-5515 to G1-5516
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// See ARM DDI 0406C.d, page B1-1182
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new |= (old & PSR_AA32_A_BIT);
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if (mode != PSR_AA32_MODE_UND && mode != PSR_AA32_MODE_SVC)
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new |= PSR_AA32_A_BIT;
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// CPSR.I is set upon any exception
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// See ARM DDI 0487E.a, pages G1-5515 to G1-5516
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// See ARM DDI 0406C.d, page B1-1182
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new |= PSR_AA32_I_BIT;
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// CPSR.F is set upon an exception to FIQ
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// CPSR.F is unchanged upon an exception to other modes
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// See ARM DDI 0487E.a, pages G1-5515 to G1-5516
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// See ARM DDI 0406C.d, page B1-1182
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new |= (old & PSR_AA32_F_BIT);
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if (mode == PSR_AA32_MODE_FIQ)
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new |= PSR_AA32_F_BIT;
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// CPSR.T is set to SCTLR.TE upon any exception
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// See ARM DDI 0487E.a, page G8-5514
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// See ARM DDI 0406C.d, page B1-1181
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if (sctlr & BIT(30))
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new |= PSR_AA32_T_BIT;
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new |= mode;
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return new;
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}
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/*
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* Table taken from ARMv8 ARM DDI0487B-B, table G1-10.
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*/
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static const u8 return_offsets[8][2] = {
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[0] = { 0, 0 }, /* Reset, unused */
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[1] = { 4, 2 }, /* Undefined */
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[2] = { 0, 0 }, /* SVC, unused */
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[3] = { 4, 4 }, /* Prefetch abort */
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[4] = { 8, 8 }, /* Data abort */
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[5] = { 0, 0 }, /* HVC, unused */
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[6] = { 4, 4 }, /* IRQ, unused */
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[7] = { 4, 4 }, /* FIQ, unused */
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};
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static void enter_exception32(struct kvm_vcpu *vcpu, u32 mode, u32 vect_offset)
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{
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unsigned long spsr = *vcpu_cpsr(vcpu);
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bool is_thumb = (spsr & PSR_AA32_T_BIT);
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u32 sctlr = __vcpu_read_sys_reg(vcpu, SCTLR_EL1);
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u32 return_address;
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*vcpu_cpsr(vcpu) = get_except32_cpsr(vcpu, mode);
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return_address = *vcpu_pc(vcpu);
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return_address += return_offsets[vect_offset >> 2][is_thumb];
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/* KVM only enters the ABT and UND modes, so only deal with those */
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switch(mode) {
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case PSR_AA32_MODE_ABT:
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__vcpu_write_spsr_abt(vcpu, host_spsr_to_spsr32(spsr));
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vcpu_gp_regs(vcpu)->compat_lr_abt = return_address;
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break;
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case PSR_AA32_MODE_UND:
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__vcpu_write_spsr_und(vcpu, host_spsr_to_spsr32(spsr));
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vcpu_gp_regs(vcpu)->compat_lr_und = return_address;
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break;
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}
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/* Branch to exception vector */
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if (sctlr & (1 << 13))
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vect_offset += 0xffff0000;
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else /* always have security exceptions */
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vect_offset += __vcpu_read_sys_reg(vcpu, VBAR_EL1);
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*vcpu_pc(vcpu) = vect_offset;
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}
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static void kvm_inject_exception(struct kvm_vcpu *vcpu)
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{
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if (vcpu_el1_is_32bit(vcpu)) {
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switch (vcpu->arch.flags & KVM_ARM64_EXCEPT_MASK) {
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case KVM_ARM64_EXCEPT_AA32_UND:
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enter_exception32(vcpu, PSR_AA32_MODE_UND, 4);
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break;
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case KVM_ARM64_EXCEPT_AA32_IABT:
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enter_exception32(vcpu, PSR_AA32_MODE_ABT, 12);
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break;
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case KVM_ARM64_EXCEPT_AA32_DABT:
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enter_exception32(vcpu, PSR_AA32_MODE_ABT, 16);
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break;
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default:
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/* Err... */
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break;
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}
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} else {
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switch (vcpu->arch.flags & KVM_ARM64_EXCEPT_MASK) {
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case (KVM_ARM64_EXCEPT_AA64_ELx_SYNC |
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KVM_ARM64_EXCEPT_AA64_EL1):
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enter_exception64(vcpu, PSR_MODE_EL1h, except_type_sync);
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break;
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default:
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/*
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* Only EL1_SYNC makes sense so far, EL2_{SYNC,IRQ}
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* will be implemented at some point. Everything
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* else gets silently ignored.
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*/
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break;
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}
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}
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}
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/*
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* Adjust the guest PC (and potentially exception state) depending on
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* flags provided by the emulation code.
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*/
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void __kvm_adjust_pc(struct kvm_vcpu *vcpu)
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{
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if (vcpu->arch.flags & KVM_ARM64_PENDING_EXCEPTION) {
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kvm_inject_exception(vcpu);
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vcpu->arch.flags &= ~(KVM_ARM64_PENDING_EXCEPTION |
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KVM_ARM64_EXCEPT_MASK);
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} else if (vcpu->arch.flags & KVM_ARM64_INCREMENT_PC) {
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kvm_skip_instr(vcpu);
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vcpu->arch.flags &= ~KVM_ARM64_INCREMENT_PC;
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}
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}
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