264 lines
6.7 KiB
C
264 lines
6.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* alternative runtime patching
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* inspired by the x86 version
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*
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* Copyright (C) 2014 ARM Ltd.
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*/
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#define pr_fmt(fmt) "alternatives: " fmt
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#include <linux/init.h>
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#include <linux/cpu.h>
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#include <asm/cacheflush.h>
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#include <asm/alternative.h>
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#include <asm/cpufeature.h>
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#include <asm/insn.h>
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#include <asm/sections.h>
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#include <linux/stop_machine.h>
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#define __ALT_PTR(a, f) ((void *)&(a)->f + (a)->f)
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#define ALT_ORIG_PTR(a) __ALT_PTR(a, orig_offset)
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#define ALT_REPL_PTR(a) __ALT_PTR(a, alt_offset)
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/* Volatile, as we may be patching the guts of READ_ONCE() */
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static volatile int all_alternatives_applied;
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static DECLARE_BITMAP(applied_alternatives, ARM64_NCAPS);
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struct alt_region {
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struct alt_instr *begin;
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struct alt_instr *end;
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};
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bool alternative_is_applied(u16 cpufeature)
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{
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if (WARN_ON(cpufeature >= ARM64_NCAPS))
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return false;
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return test_bit(cpufeature, applied_alternatives);
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}
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/*
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* Check if the target PC is within an alternative block.
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*/
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static __always_inline bool branch_insn_requires_update(struct alt_instr *alt, unsigned long pc)
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{
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unsigned long replptr = (unsigned long)ALT_REPL_PTR(alt);
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return !(pc >= replptr && pc <= (replptr + alt->alt_len));
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}
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#define align_down(x, a) ((unsigned long)(x) & ~(((unsigned long)(a)) - 1))
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static __always_inline u32 get_alt_insn(struct alt_instr *alt, __le32 *insnptr, __le32 *altinsnptr)
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{
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u32 insn;
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insn = le32_to_cpu(*altinsnptr);
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if (aarch64_insn_is_branch_imm(insn)) {
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s32 offset = aarch64_get_branch_offset(insn);
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unsigned long target;
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target = (unsigned long)altinsnptr + offset;
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/*
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* If we're branching inside the alternate sequence,
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* do not rewrite the instruction, as it is already
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* correct. Otherwise, generate the new instruction.
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*/
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if (branch_insn_requires_update(alt, target)) {
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offset = target - (unsigned long)insnptr;
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insn = aarch64_set_branch_offset(insn, offset);
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}
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} else if (aarch64_insn_is_adrp(insn)) {
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s32 orig_offset, new_offset;
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unsigned long target;
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/*
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* If we're replacing an adrp instruction, which uses PC-relative
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* immediate addressing, adjust the offset to reflect the new
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* PC. adrp operates on 4K aligned addresses.
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*/
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orig_offset = aarch64_insn_adrp_get_offset(insn);
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target = align_down(altinsnptr, SZ_4K) + orig_offset;
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new_offset = target - align_down(insnptr, SZ_4K);
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insn = aarch64_insn_adrp_set_offset(insn, new_offset);
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} else if (aarch64_insn_uses_literal(insn)) {
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/*
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* Disallow patching unhandled instructions using PC relative
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* literal addresses
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*/
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BUG();
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}
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return insn;
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}
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static noinstr void patch_alternative(struct alt_instr *alt,
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__le32 *origptr, __le32 *updptr, int nr_inst)
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{
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__le32 *replptr;
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int i;
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replptr = ALT_REPL_PTR(alt);
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for (i = 0; i < nr_inst; i++) {
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u32 insn;
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insn = get_alt_insn(alt, origptr + i, replptr + i);
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updptr[i] = cpu_to_le32(insn);
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}
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}
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/*
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* We provide our own, private D-cache cleaning function so that we don't
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* accidentally call into the cache.S code, which is patched by us at
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* runtime.
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*/
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static void clean_dcache_range_nopatch(u64 start, u64 end)
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{
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u64 cur, d_size, ctr_el0;
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ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0);
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d_size = 4 << cpuid_feature_extract_unsigned_field(ctr_el0,
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CTR_DMINLINE_SHIFT);
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cur = start & ~(d_size - 1);
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do {
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/*
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* We must clean+invalidate to the PoC in order to avoid
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* Cortex-A53 errata 826319, 827319, 824069 and 819472
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* (this corresponds to ARM64_WORKAROUND_CLEAN_CACHE)
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*/
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asm volatile("dc civac, %0" : : "r" (cur) : "memory");
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} while (cur += d_size, cur < end);
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}
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static void __nocfi __apply_alternatives(struct alt_region *region, bool is_module,
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unsigned long *feature_mask)
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{
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struct alt_instr *alt;
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__le32 *origptr, *updptr;
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alternative_cb_t alt_cb;
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for (alt = region->begin; alt < region->end; alt++) {
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int nr_inst;
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if (!test_bit(alt->cpufeature, feature_mask))
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continue;
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/* Use ARM64_CB_PATCH as an unconditional patch */
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if (alt->cpufeature < ARM64_CB_PATCH &&
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!cpus_have_cap(alt->cpufeature))
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continue;
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if (alt->cpufeature == ARM64_CB_PATCH)
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BUG_ON(alt->alt_len != 0);
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else
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BUG_ON(alt->alt_len != alt->orig_len);
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pr_info_once("patching kernel code\n");
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origptr = ALT_ORIG_PTR(alt);
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updptr = is_module ? origptr : lm_alias(origptr);
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nr_inst = alt->orig_len / AARCH64_INSN_SIZE;
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if (alt->cpufeature < ARM64_CB_PATCH)
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alt_cb = patch_alternative;
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else
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alt_cb = ALT_REPL_PTR(alt);
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alt_cb(alt, origptr, updptr, nr_inst);
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if (!is_module) {
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clean_dcache_range_nopatch((u64)origptr,
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(u64)(origptr + nr_inst));
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}
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}
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/*
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* The core module code takes care of cache maintenance in
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* flush_module_icache().
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*/
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if (!is_module) {
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dsb(ish);
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icache_inval_all_pou();
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isb();
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/* Ignore ARM64_CB bit from feature mask */
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bitmap_or(applied_alternatives, applied_alternatives,
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feature_mask, ARM64_NCAPS);
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bitmap_and(applied_alternatives, applied_alternatives,
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cpu_hwcaps, ARM64_NCAPS);
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}
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}
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/*
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* We might be patching the stop_machine state machine, so implement a
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* really simple polling protocol here.
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*/
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static int __apply_alternatives_multi_stop(void *unused)
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{
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struct alt_region region = {
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.begin = (struct alt_instr *)__alt_instructions,
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.end = (struct alt_instr *)__alt_instructions_end,
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};
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/* We always have a CPU 0 at this point (__init) */
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if (smp_processor_id()) {
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while (!all_alternatives_applied)
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cpu_relax();
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isb();
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} else {
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DECLARE_BITMAP(remaining_capabilities, ARM64_NPATCHABLE);
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bitmap_complement(remaining_capabilities, boot_capabilities,
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ARM64_NPATCHABLE);
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BUG_ON(all_alternatives_applied);
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__apply_alternatives(®ion, false, remaining_capabilities);
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/* Barriers provided by the cache flushing */
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all_alternatives_applied = 1;
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}
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return 0;
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}
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void __init apply_alternatives_all(void)
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{
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/* better not try code patching on a live SMP system */
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stop_machine(__apply_alternatives_multi_stop, NULL, cpu_online_mask);
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}
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/*
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* This is called very early in the boot process (directly after we run
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* a feature detect on the boot CPU). No need to worry about other CPUs
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* here.
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*/
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void __init apply_boot_alternatives(void)
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{
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struct alt_region region = {
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.begin = (struct alt_instr *)__alt_instructions,
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.end = (struct alt_instr *)__alt_instructions_end,
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};
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/* If called on non-boot cpu things could go wrong */
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WARN_ON(smp_processor_id() != 0);
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__apply_alternatives(®ion, false, &boot_capabilities[0]);
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}
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#ifdef CONFIG_MODULES
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void apply_alternatives_module(void *start, size_t length)
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{
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struct alt_region region = {
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.begin = start,
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.end = start + length,
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};
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DECLARE_BITMAP(all_capabilities, ARM64_NPATCHABLE);
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bitmap_fill(all_capabilities, ARM64_NPATCHABLE);
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__apply_alternatives(®ion, true, &all_capabilities[0]);
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}
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#endif
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