204 lines
5.2 KiB
C
204 lines
5.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*/
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#ifndef __ARM_KVM_INIT_H__
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#define __ARM_KVM_INIT_H__
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#ifndef __ASSEMBLY__
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#error Assembly-only header
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#endif
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#include <asm/kvm_arm.h>
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#include <asm/ptrace.h>
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#include <asm/sysreg.h>
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#include <linux/irqchip/arm-gic-v3.h>
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.macro __init_el2_sctlr
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mov_q x0, INIT_SCTLR_EL2_MMU_OFF
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msr sctlr_el2, x0
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isb
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.endm
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/*
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* Allow Non-secure EL1 and EL0 to access physical timer and counter.
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* This is not necessary for VHE, since the host kernel runs in EL2,
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* and EL0 accesses are configured in the later stage of boot process.
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* Note that when HCR_EL2.E2H == 1, CNTHCTL_EL2 has the same bit layout
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* as CNTKCTL_EL1, and CNTKCTL_EL1 accessing instructions are redefined
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* to access CNTHCTL_EL2. This allows the kernel designed to run at EL1
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* to transparently mess with the EL0 bits via CNTKCTL_EL1 access in
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* EL2.
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*/
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.macro __init_el2_timers
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mov x0, #3 // Enable EL1 physical timers
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msr cnthctl_el2, x0
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msr cntvoff_el2, xzr // Clear virtual offset
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.endm
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.macro __init_el2_debug
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mrs x1, id_aa64dfr0_el1
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sbfx x0, x1, #ID_AA64DFR0_PMUVER_SHIFT, #4
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cmp x0, #1
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b.lt .Lskip_pmu_\@ // Skip if no PMU present
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mrs x0, pmcr_el0 // Disable debug access traps
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ubfx x0, x0, #11, #5 // to EL2 and allow access to
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.Lskip_pmu_\@:
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csel x2, xzr, x0, lt // all PMU counters from EL1
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/* Statistical profiling */
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ubfx x0, x1, #ID_AA64DFR0_PMSVER_SHIFT, #4
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cbz x0, .Lskip_spe_\@ // Skip if SPE not present
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mrs_s x0, SYS_PMBIDR_EL1 // If SPE available at EL2,
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and x0, x0, #(1 << SYS_PMBIDR_EL1_P_SHIFT)
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cbnz x0, .Lskip_spe_el2_\@ // then permit sampling of physical
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mov x0, #(1 << SYS_PMSCR_EL2_PCT_SHIFT | \
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1 << SYS_PMSCR_EL2_PA_SHIFT)
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msr_s SYS_PMSCR_EL2, x0 // addresses and physical counter
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.Lskip_spe_el2_\@:
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mov x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT)
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orr x2, x2, x0 // If we don't have VHE, then
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// use EL1&0 translation.
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.Lskip_spe_\@:
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/* Trace buffer */
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ubfx x0, x1, #ID_AA64DFR0_TRBE_SHIFT, #4
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cbz x0, .Lskip_trace_\@ // Skip if TraceBuffer is not present
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mrs_s x0, SYS_TRBIDR_EL1
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and x0, x0, TRBIDR_PROG
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cbnz x0, .Lskip_trace_\@ // If TRBE is available at EL2
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mov x0, #(MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT)
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orr x2, x2, x0 // allow the EL1&0 translation
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// to own it.
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.Lskip_trace_\@:
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msr mdcr_el2, x2 // Configure debug traps
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.endm
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/* LORegions */
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.macro __init_el2_lor
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mrs x1, id_aa64mmfr1_el1
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ubfx x0, x1, #ID_AA64MMFR1_LOR_SHIFT, 4
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cbz x0, .Lskip_lor_\@
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msr_s SYS_LORC_EL1, xzr
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.Lskip_lor_\@:
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.endm
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/* Stage-2 translation */
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.macro __init_el2_stage2
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msr vttbr_el2, xzr
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.endm
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/* GICv3 system register access */
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.macro __init_el2_gicv3
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mrs x0, id_aa64pfr0_el1
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ubfx x0, x0, #ID_AA64PFR0_GIC_SHIFT, #4
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cbz x0, .Lskip_gicv3_\@
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mrs_s x0, SYS_ICC_SRE_EL2
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orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
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orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
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msr_s SYS_ICC_SRE_EL2, x0
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isb // Make sure SRE is now set
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mrs_s x0, SYS_ICC_SRE_EL2 // Read SRE back,
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tbz x0, #0, .Lskip_gicv3_\@ // and check that it sticks
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msr_s SYS_ICH_HCR_EL2, xzr // Reset ICH_HCR_EL2 to defaults
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.Lskip_gicv3_\@:
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.endm
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.macro __init_el2_hstr
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msr hstr_el2, xzr // Disable CP15 traps to EL2
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.endm
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/* Virtual CPU ID registers */
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.macro __init_el2_nvhe_idregs
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mrs x0, midr_el1
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mrs x1, mpidr_el1
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msr vpidr_el2, x0
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msr vmpidr_el2, x1
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.endm
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/* Coprocessor traps */
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.macro __init_el2_nvhe_cptr
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mov x0, #0x33ff
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msr cptr_el2, x0 // Disable copro. traps to EL2
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.endm
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/* SVE register access */
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.macro __init_el2_nvhe_sve
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mrs x1, id_aa64pfr0_el1
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ubfx x1, x1, #ID_AA64PFR0_SVE_SHIFT, #4
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cbz x1, .Lskip_sve_\@
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bic x0, x0, #CPTR_EL2_TZ // Also disable SVE traps
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msr cptr_el2, x0 // Disable copro. traps to EL2
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isb
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mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector
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msr_s SYS_ZCR_EL2, x1 // length for EL1.
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.Lskip_sve_\@:
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.endm
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/* Disable any fine grained traps */
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.macro __init_el2_fgt
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mrs x1, id_aa64mmfr0_el1
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ubfx x1, x1, #ID_AA64MMFR0_FGT_SHIFT, #4
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cbz x1, .Lskip_fgt_\@
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mov x0, xzr
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mrs x1, id_aa64dfr0_el1
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ubfx x1, x1, #ID_AA64DFR0_PMSVER_SHIFT, #4
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cmp x1, #3
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b.lt .Lset_fgt_\@
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/* Disable PMSNEVFR_EL1 read and write traps */
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orr x0, x0, #(1 << 62)
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.Lset_fgt_\@:
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msr_s SYS_HDFGRTR_EL2, x0
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msr_s SYS_HDFGWTR_EL2, x0
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msr_s SYS_HFGRTR_EL2, xzr
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msr_s SYS_HFGWTR_EL2, xzr
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msr_s SYS_HFGITR_EL2, xzr
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mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU
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ubfx x1, x1, #ID_AA64PFR0_AMU_SHIFT, #4
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cbz x1, .Lskip_fgt_\@
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msr_s SYS_HAFGRTR_EL2, xzr
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.Lskip_fgt_\@:
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.endm
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.macro __init_el2_nvhe_prepare_eret
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mov x0, #INIT_PSTATE_EL1
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msr spsr_el2, x0
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.endm
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/**
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* Initialize EL2 registers to sane values. This should be called early on all
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* cores that were booted in EL2. Note that everything gets initialised as
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* if VHE was not evailable. The kernel context will be upgraded to VHE
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* if possible later on in the boot process
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*
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* Regs: x0, x1 and x2 are clobbered.
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*/
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.macro init_el2_state
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__init_el2_sctlr
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__init_el2_timers
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__init_el2_debug
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__init_el2_lor
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__init_el2_stage2
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__init_el2_gicv3
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__init_el2_hstr
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__init_el2_nvhe_idregs
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__init_el2_nvhe_cptr
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__init_el2_nvhe_sve
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__init_el2_fgt
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__init_el2_nvhe_prepare_eret
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.endm
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#endif /* __ARM_KVM_INIT_H__ */
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