208 lines
6.0 KiB
Plaintext
208 lines
6.0 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 or MIT)
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/*
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* Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*/
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#include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/r8a779f0-sysc.h>
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/ {
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compatible = "renesas,r8a779f0";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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a55_0: cpu@0 {
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compatible = "arm,cortex-a55";
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reg = <0>;
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device_type = "cpu";
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power-domains = <&sysc R8A779F0_PD_A1E0D0C0>;
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};
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};
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extal_clk: extal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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extalr_clk: extalr {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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pmu_a55 {
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compatible = "arm,cortex-a55-pmu";
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interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
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};
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/* External SCIF clock - to be overridden by boards that provide it */
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scif_clk: scif {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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soc: soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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rwdt: watchdog@e6020000 {
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compatible = "renesas,r8a779f0-wdt",
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"renesas,rcar-gen4-wdt";
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reg = <0 0xe6020000 0 0x0c>;
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clocks = <&cpg CPG_MOD 907>;
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power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
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resets = <&cpg 907>;
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status = "disabled";
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};
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pfc: pinctrl@e6050000 {
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compatible = "renesas,pfc-r8a779f0";
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reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
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<0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>;
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};
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a779f0-cpg-mssr";
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reg = <0 0xe6150000 0 0x4000>;
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clocks = <&extal_clk>, <&extalr_clk>;
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clock-names = "extal", "extalr";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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};
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rst: reset-controller@e6160000 {
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compatible = "renesas,r8a779f0-rst";
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reg = <0 0xe6160000 0 0x4000>;
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a779f0-sysc";
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reg = <0 0xe6180000 0 0x4000>;
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#power-domain-cells = <1>;
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};
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scif3: serial@e6c50000 {
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compatible = "renesas,scif-r8a779f0",
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"renesas,rcar-gen4-scif", "renesas,scif";
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reg = <0 0xe6c50000 0 64>;
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interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 704>,
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<&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
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resets = <&cpg 704>;
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status = "disabled";
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};
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dmac0: dma-controller@e7350000 {
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compatible = "renesas,dmac-r8a779f0",
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"renesas,rcar-gen4-dmac";
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reg = <0 0xe7350000 0 0x1000>,
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<0 0xe7300000 0 0x10000>;
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3", "ch4",
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"ch5", "ch6", "ch7", "ch8", "ch9",
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"ch10", "ch11", "ch12", "ch13",
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"ch14", "ch15";
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clocks = <&cpg CPG_MOD 709>;
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clock-names = "fck";
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power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
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resets = <&cpg 709>;
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#dma-cells = <1>;
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dma-channels = <16>;
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};
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dmac1: dma-controller@e7351000 {
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compatible = "renesas,dmac-r8a779f0",
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"renesas,rcar-gen4-dmac";
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reg = <0 0xe7351000 0 0x1000>,
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<0 0xe7310000 0 0x10000>;
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interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3", "ch4",
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"ch5", "ch6", "ch7", "ch8", "ch9",
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"ch10", "ch11", "ch12", "ch13",
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"ch14", "ch15";
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clocks = <&cpg CPG_MOD 710>;
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clock-names = "fck";
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power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
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resets = <&cpg 710>;
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#dma-cells = <1>;
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dma-channels = <16>;
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};
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gic: interrupt-controller@f1000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x0 0xf1000000 0 0x20000>,
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<0x0 0xf1060000 0 0x110000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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prr: chipid@fff00044 {
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compatible = "renesas,prr";
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reg = <0 0xfff00044 0 4>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
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};
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};
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