65 lines
1.2 KiB
Plaintext
65 lines
1.2 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2021 NXP
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*/
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/dts-v1/;
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#include "imx8ulp.dtsi"
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/ {
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model = "NXP i.MX8ULP EVK";
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compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
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chosen {
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stdout-path = &lpuart5;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0 0x80000000>;
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};
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};
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&lpuart5 {
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/* console */
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_lpuart5>;
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pinctrl-1 = <&pinctrl_lpuart5>;
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status = "okay";
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};
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&usdhc0 {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_usdhc0>;
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pinctrl-1 = <&pinctrl_usdhc0>;
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non-removable;
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bus-width = <8>;
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status = "okay";
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};
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&iomuxc1 {
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pinctrl_lpuart5: lpuart5grp {
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fsl,pins = <
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MX8ULP_PAD_PTF14__LPUART5_TX 0x3
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MX8ULP_PAD_PTF15__LPUART5_RX 0x3
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>;
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};
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pinctrl_usdhc0: usdhc0grp {
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fsl,pins = <
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MX8ULP_PAD_PTD1__SDHC0_CMD 0x43
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MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042
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MX8ULP_PAD_PTD10__SDHC0_D0 0x43
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MX8ULP_PAD_PTD9__SDHC0_D1 0x43
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MX8ULP_PAD_PTD8__SDHC0_D2 0x43
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MX8ULP_PAD_PTD7__SDHC0_D3 0x43
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MX8ULP_PAD_PTD6__SDHC0_D4 0x43
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MX8ULP_PAD_PTD5__SDHC0_D5 0x43
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MX8ULP_PAD_PTD4__SDHC0_D6 0x43
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MX8ULP_PAD_PTD3__SDHC0_D7 0x43
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MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042
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>;
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};
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};
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