295 lines
7.9 KiB
Plaintext
295 lines
7.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree for the ARM Integrator/AP platform
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*/
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/dts-v1/;
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#include "integrator.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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model = "ARM Integrator/AP";
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compatible = "arm,integrator-ap";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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/*
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* Since the board has pluggable CPU modules, we
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* cannot define a proper compatible here. Let the
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* boot loader fill in the apropriate compatible
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* string if necessary.
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*/
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/* compatible = "arm,arm926ej-s"; */
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reg = <0>;
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/*
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* The documentation in ARM DUI 0138E page 3-12 states
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* that the maximum frequency for this clock is 200 MHz
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* but painful trial-and-error has proved to me that it
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* is actually just hanging the system above 71 MHz.
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* Sad but true.
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*/
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/* kHz uV */
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operating-points = <71000 0
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66000 0
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60000 0
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48000 0
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36000 0
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24000 0
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12000 0>;
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clocks = <&cmosc>;
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clock-names = "cpu";
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clock-latency = <1000000>; /* 1 ms */
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};
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};
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aliases {
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arm,timer-primary = &timer2;
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arm,timer-secondary = &timer1;
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};
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chosen {
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bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
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};
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/* 24 MHz chrystal on the Integrator/AP development board */
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xtal24mhz: xtal24mhz@24M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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pclk: pclk@0 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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/* The UART clock is 14.74 MHz divided by an ICS525 */
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uartclk: uartclk@14.74M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <14745600>;
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clocks = <&xtal24mhz>;
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};
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core-module@10000000 {
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/* 24 MHz chrystal on the core module */
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cm24mhz: cm24mhz@24M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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/* Oscillator on the core module, clocks the CPU core */
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cmosc: clock-controller@8 {
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compatible = "arm,syscon-icst525-integratorap-cm";
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reg = <0x08 0x04>;
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#clock-cells = <0>;
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lock-offset = <0x14>;
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vco-offset = <0x08>;
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clocks = <&cm24mhz>;
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};
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/* Auxilary oscillator on the core module, 32.369MHz at boot */
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auxosc: clock-controller@1c {
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compatible = "arm,syscon-icst525";
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reg = <0x1c 0x04>;
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#clock-cells = <0>;
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lock-offset = <0x14>;
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vco-offset = <0x1c>;
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clocks = <&cm24mhz>;
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};
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};
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syscon {
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compatible = "arm,integrator-ap-syscon", "syscon";
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reg = <0x11000000 0x100>;
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ranges = <0x0 0x11000000 0x100>;
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#size-cells = <1>;
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#address-cells = <1>;
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/*
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* SYSCLK clocks PCIv3 bridge, system controller and the
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* logic modules.
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*/
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sysclk: clock-controller@4 {
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compatible = "arm,syscon-icst525-integratorap-sys";
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reg = <0x04 0x04>;
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#clock-cells = <0>;
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lock-offset = <0x1c>;
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vco-offset = <0x04>;
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clocks = <&xtal24mhz>;
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};
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/* One-bit control for the PCI bus clock (33 or 25 MHz) */
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pciclk: clock-controller@4,8 {
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compatible = "arm,syscon-icst525-integratorap-pci";
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reg = <0x04 0x04>;
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#clock-cells = <0>;
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lock-offset = <0x1c>;
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vco-offset = <0x04>;
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clocks = <&xtal24mhz>;
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};
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};
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timer0: timer@13000000 {
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compatible = "arm,integrator-timer";
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clocks = <&xtal24mhz>;
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};
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timer1: timer@13000100 {
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compatible = "arm,integrator-timer";
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clocks = <&xtal24mhz>;
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};
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timer2: timer@13000200 {
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compatible = "arm,integrator-timer";
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clocks = <&xtal24mhz>;
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};
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pic: pic@14000000 {
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valid-mask = <0x003fffff>;
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};
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pci: pciv3@62000000 {
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compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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/* Bridge registers and config access space */
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reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
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interrupt-parent = <&pic>;
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interrupts = <17>; /* Bus error IRQ */
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clocks = <&pciclk>;
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bus-range = <0x00 0xff>;
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ranges = <0x01000000 0 0x0000000 /* I/O space @00000000 */
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0x60000000 0 0x00010000 /* 64 KB @ LB 60000000 */
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0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
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0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
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0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
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0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
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dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
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0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */
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0x02000000 0 0x80000000 /* Core module alias memory */
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0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */
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interrupt-map-mask = <0xf800 0 0 0x7>;
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interrupt-map = <
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/* IDSEL 9 */
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0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
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0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
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0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
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0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
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/* IDSEL 10 */
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0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
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0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
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0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
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0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
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/* IDSEL 11 */
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0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
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0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
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0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
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0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
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/* IDSEL 12 */
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0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
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0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
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0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
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0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
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>;
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};
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fpga {
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/*
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* The Integator/AP predates the idea to have magic numbers
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* identifying the PrimeCell in hardware, thus we have to
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* supply these from the device tree.
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*/
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rtc: rtc@15000000 {
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compatible = "arm,pl030", "arm,primecell";
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arm,primecell-periphid = <0x00041030>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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uart0: uart@16000000 {
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compatible = "arm,pl010", "arm,primecell";
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arm,primecell-periphid = <0x00041010>;
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clocks = <&uartclk>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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uart1: uart@17000000 {
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compatible = "arm,pl010", "arm,primecell";
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arm,primecell-periphid = <0x00041010>;
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clocks = <&uartclk>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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kmi0: kmi@18000000 {
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compatible = "arm,pl050", "arm,primecell";
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arm,primecell-periphid = <0x00041050>;
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clocks = <&xtal24mhz>, <&pclk>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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kmi1: kmi@19000000 {
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compatible = "arm,pl050", "arm,primecell";
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arm,primecell-periphid = <0x00041050>;
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clocks = <&xtal24mhz>, <&pclk>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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};
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/*
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* Logic module bus, we support up to 4 logical modules
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* They appear at 0xc0000000, 0xd0000000, 0xe0000000 and 0xf0000000
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* and use interrupts 9, 10, 11 and 12 respectively.
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*/
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bus@c0000000 {
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compatible = "arm,integrator-ap-lm";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0xc0000000 0xc0000000 0x40000000>;
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dma-ranges;
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lm0: bus@c0000000 {
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compatible = "simple-bus";
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ranges = <0x00000000 0xc0000000 0x10000000>;
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dma-ranges = <0x00000000 0x80000000 0x10000000>;
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reg = <0xc0000000 0x10000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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lm1: bus@d0000000 {
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compatible = "simple-bus";
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ranges = <0x00000000 0xd0000000 0x10000000>;
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dma-ranges = <0x00000000 0x80000000 0x10000000>;
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reg = <0xd0000000 0x10000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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lm2: bus@e0000000 {
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compatible = "simple-bus";
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ranges = <0x00000000 0xe0000000 0x10000000>;
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dma-ranges = <0x00000000 0x80000000 0x10000000>;
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reg = <0xe0000000 0x10000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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lm3: bus@f0000000 {
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compatible = "simple-bus";
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ranges = <0x00000000 0xf0000000 0x10000000>;
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dma-ranges = <0x00000000 0x80000000 0x10000000>;
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reg = <0xf0000000 0x10000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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};
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