380 lines
9.0 KiB
Plaintext
380 lines
9.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
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&pllss {
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/*
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* See TRM "2.6.10 Connected outputso DPLLS" and
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* "2.6.11 Connected Outputs of DPLLJ". Only clkout is
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* connected except for hdmi and usb.
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*/
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adpll_mpu_ck: adpll@40 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-s-clock";
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reg = <0x40 0x40>;
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clocks = <&devosc_ck &devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow", "clkinphif";
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clock-output-names = "481c5040.adpll.dcoclkldo",
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"481c5040.adpll.clkout",
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"481c5040.adpll.clkoutx2",
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"481c5040.adpll.clkouthif";
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};
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adpll_dsp_ck: adpll@80 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-lj-clock";
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reg = <0x80 0x30>;
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clocks = <&devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow";
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clock-output-names = "481c5080.adpll.dcoclkldo",
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"481c5080.adpll.clkout",
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"481c5080.adpll.clkoutldo";
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};
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adpll_sgx_ck: adpll@b0 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-lj-clock";
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reg = <0xb0 0x30>;
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clocks = <&devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow";
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clock-output-names = "481c50b0.adpll.dcoclkldo",
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"481c50b0.adpll.clkout",
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"481c50b0.adpll.clkoutldo";
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};
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adpll_hdvic_ck: adpll@e0 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-lj-clock";
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reg = <0xe0 0x30>;
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clocks = <&devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow";
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clock-output-names = "481c50e0.adpll.dcoclkldo",
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"481c50e0.adpll.clkout",
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"481c50e0.adpll.clkoutldo";
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};
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adpll_l3_ck: adpll@110 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-lj-clock";
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reg = <0x110 0x30>;
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clocks = <&devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow";
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clock-output-names = "481c5110.adpll.dcoclkldo",
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"481c5110.adpll.clkout",
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"481c5110.adpll.clkoutldo";
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};
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adpll_isp_ck: adpll@140 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-lj-clock";
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reg = <0x140 0x30>;
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clocks = <&devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow";
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clock-output-names = "481c5140.adpll.dcoclkldo",
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"481c5140.adpll.clkout",
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"481c5140.adpll.clkoutldo";
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};
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adpll_dss_ck: adpll@170 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-lj-clock";
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reg = <0x170 0x30>;
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clocks = <&devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow";
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clock-output-names = "481c5170.adpll.dcoclkldo",
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"481c5170.adpll.clkout",
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"481c5170.adpll.clkoutldo";
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};
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adpll_video0_ck: adpll@1a0 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-lj-clock";
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reg = <0x1a0 0x30>;
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clocks = <&devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow";
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clock-output-names = "481c51a0.adpll.dcoclkldo",
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"481c51a0.adpll.clkout",
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"481c51a0.adpll.clkoutldo";
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};
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adpll_video1_ck: adpll@1d0 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-lj-clock";
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reg = <0x1d0 0x30>;
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clocks = <&devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow";
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clock-output-names = "481c51d0.adpll.dcoclkldo",
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"481c51d0.adpll.clkout",
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"481c51d0.adpll.clkoutldo";
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};
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adpll_hdmi_ck: adpll@200 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-lj-clock";
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reg = <0x200 0x30>;
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clocks = <&devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow";
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clock-output-names = "481c5200.adpll.dcoclkldo",
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"481c5200.adpll.clkout",
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"481c5200.adpll.clkoutldo";
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};
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adpll_audio_ck: adpll@230 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-lj-clock";
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reg = <0x230 0x30>;
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clocks = <&devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow";
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clock-output-names = "481c5230.adpll.dcoclkldo",
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"481c5230.adpll.clkout",
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"481c5230.adpll.clkoutldo";
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};
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adpll_usb_ck: adpll@260 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-lj-clock";
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reg = <0x260 0x30>;
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clocks = <&devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow";
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clock-output-names = "481c5260.adpll.dcoclkldo",
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"481c5260.adpll.clkout",
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"481c5260.adpll.clkoutldo";
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};
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adpll_ddr_ck: adpll@290 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-lj-clock";
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reg = <0x290 0x30>;
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clocks = <&devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow";
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clock-output-names = "481c5290.adpll.dcoclkldo",
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"481c5290.adpll.clkout",
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"481c5290.adpll.clkoutldo";
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};
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};
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&pllss_clocks {
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timer1_fck: timer1_fck@2e0 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
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&aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
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ti,bit-shift = <3>;
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reg = <0x2e0>;
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};
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timer2_fck: timer2_fck@2e0 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
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&aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
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ti,bit-shift = <6>;
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reg = <0x2e0>;
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};
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/* CPTS_RFT_CLK in RMII_REFCLK_SRC, usually sourced from auiod */
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cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&adpll_video0_ck 1
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&adpll_video1_ck 1
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&adpll_audio_ck 1>;
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ti,bit-shift = <1>;
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reg = <0x2e8>;
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};
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/* REVISIT: Set up with a proper mux using RMII_REFCLK_SRC */
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cpsw_125mhz_gclk: cpsw_125mhz_gclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <125000000>;
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};
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sysclk18_ck: sysclk18_ck@2f0 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&rtcosc_ck>, <&rtcdivider_ck>;
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ti,bit-shift = <0>;
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reg = <0x02f0>;
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};
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};
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&scm_clocks {
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devosc_ck: devosc_ck@40 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&virt_20000000_ck>, <&virt_19200000_ck>;
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ti,bit-shift = <21>;
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reg = <0x0040>;
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};
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/* Optional auxosc, 20 - 30 MHz range, assume 22.5729 MHz by default */
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auxosc_ck: auxosc_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <22572900>;
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};
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/* Optional 32768Hz crystal or clock on RTCOSC pins */
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rtcosc_ck: rtcosc_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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/* Optional external clock on TCLKIN pin, set rate in baord dts file */
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tclkin_ck: tclkin_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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virt_20000000_ck: virt_20000000_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <20000000>;
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};
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virt_19200000_ck: virt_19200000_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <19200000>;
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};
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mpu_ck: mpu_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <1000000000>;
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};
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};
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&prcm_clocks {
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osc_src_ck: osc_src_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&devosc_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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mpu_clksrc_ck: mpu_clksrc_ck@40 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&devosc_ck>, <&rtcdivider_ck>;
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ti,bit-shift = <0>;
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reg = <0x0040>;
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};
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/* Fixed divider clock 0.0016384 * devosc */
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rtcdivider_ck: rtcdivider_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&devosc_ck>;
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clock-mult = <128>;
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clock-div = <78125>;
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};
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/* L4_HS 220 MHz*/
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sysclk4_ck: sysclk4_ck {
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#clock-cells = <0>;
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compatible = "ti,fixed-factor-clock";
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clocks = <&adpll_l3_ck 1>;
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ti,clock-mult = <1>;
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ti,clock-div = <1>;
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};
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/* L4_FWCFG */
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sysclk5_ck: sysclk5_ck {
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#clock-cells = <0>;
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compatible = "ti,fixed-factor-clock";
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clocks = <&adpll_l3_ck 1>;
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ti,clock-mult = <1>;
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ti,clock-div = <2>;
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};
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/* L4_LS 110 MHz */
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sysclk6_ck: sysclk6_ck {
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#clock-cells = <0>;
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compatible = "ti,fixed-factor-clock";
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clocks = <&adpll_l3_ck 1>;
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ti,clock-mult = <1>;
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ti,clock-div = <2>;
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};
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sysclk8_ck: sysclk8_ck {
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#clock-cells = <0>;
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compatible = "ti,fixed-factor-clock";
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clocks = <&adpll_usb_ck 1>;
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ti,clock-mult = <1>;
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ti,clock-div = <1>;
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};
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sysclk10_ck: sysclk10_ck {
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compatible = "ti,divider-clock";
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reg = <0x324>;
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ti,max-div = <7>;
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#clock-cells = <0>;
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clocks = <&adpll_usb_ck 1>;
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};
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aud_clkin0_ck: aud_clkin0_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <20000000>;
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};
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aud_clkin1_ck: aud_clkin1_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <20000000>;
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};
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aud_clkin2_ck: aud_clkin2_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <20000000>;
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};
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};
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&prcm {
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default_cm: default_cm@500 {
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compatible = "ti,omap4-cm";
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reg = <0x500 0x100>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x500 0x100>;
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default_clkctrl: clk@0 {
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compatible = "ti,clkctrl";
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reg = <0x0 0x5c>;
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#clock-cells = <2>;
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};
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};
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alwon_cm: alwon_cm@1400 {
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compatible = "ti,omap4-cm";
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reg = <0x1400 0x300>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x1400 0x300>;
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alwon_clkctrl: clk@0 {
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compatible = "ti,clkctrl";
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reg = <0x0 0x228>;
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#clock-cells = <2>;
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};
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};
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alwon_ethernet_cm: alwon_ethernet_cm@15d4 {
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compatible = "ti,omap4-cm";
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reg = <0x15d4 0x4>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x15d4 0x4>;
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alwon_ethernet_clkctrl: clk@0 {
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compatible = "ti,clkctrl";
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reg = <0 0x4>;
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#clock-cells = <2>;
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};
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};
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};
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