375 lines
5.6 KiB
Plaintext
375 lines
5.6 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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// Copyright (c) 2019 Facebook Inc.
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/dts-v1/;
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#include <dt-bindings/gpio/aspeed-gpio.h>
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#include "ast2500-facebook-netbmc-common.dtsi"
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/ {
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model = "Facebook Wedge 400 BMC";
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compatible = "facebook,wedge400-bmc", "aspeed,ast2500";
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aliases {
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/*
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* PCA9548 (2-0070) provides 8 channels connecting to
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* SCM (System Controller Module).
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*/
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i2c16 = &imux16;
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i2c17 = &imux17;
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i2c18 = &imux18;
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i2c19 = &imux19;
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i2c20 = &imux20;
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i2c21 = &imux21;
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i2c22 = &imux22;
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i2c23 = &imux23;
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/*
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* PCA9548 (8-0070) provides 8 channels connecting to
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* SMB (Switch Main Board).
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*/
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i2c24 = &imux24;
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i2c25 = &imux25;
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i2c26 = &imux26;
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i2c27 = &imux27;
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i2c28 = &imux28;
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i2c29 = &imux29;
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i2c30 = &imux30;
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i2c31 = &imux31;
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/*
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* PCA9548 (11-0076) provides 8 channels connecting to
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* FCM (Fan Controller Module).
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*/
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i2c32 = &imux32;
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i2c33 = &imux33;
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i2c34 = &imux34;
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i2c35 = &imux35;
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i2c36 = &imux36;
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i2c37 = &imux37;
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i2c38 = &imux38;
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i2c39 = &imux39;
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spi2 = &spi_gpio;
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};
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chosen {
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stdout-path = &uart1;
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bootargs = "console=ttyS0,9600n8 root=/dev/ram rw";
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};
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ast-adc-hwmon {
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compatible = "iio-hwmon";
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io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>;
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};
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/*
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* GPIO-based SPI Master is required to access SPI TPM, because
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* full-duplex SPI transactions are not supported by ASPEED SPI
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* Controllers.
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*/
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spi_gpio: spi-gpio {
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status = "okay";
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compatible = "spi-gpio";
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#address-cells = <1>;
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#size-cells = <0>;
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cs-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_LOW>;
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gpio-sck = <&gpio ASPEED_GPIO(R, 3) GPIO_ACTIVE_HIGH>;
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gpio-mosi = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_HIGH>;
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gpio-miso = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_HIGH>;
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num-chipselects = <1>;
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tpmdev@0 {
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compatible = "tcg,tpm_tis-spi";
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spi-max-frequency = <33000000>;
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reg = <0>;
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};
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};
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};
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/*
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* Both firmware flashes are 128MB on Wedge400 BMC.
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*/
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&fmc_flash0 {
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#include "facebook-bmc-flash-layout-128.dtsi"
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};
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&fmc_flash1 {
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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flash1@0 {
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reg = <0x0 0x8000000>;
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label = "flash1";
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};
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};
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};
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&uart2 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_txd2_default
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&pinctrl_rxd2_default>;
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};
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&uart4 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_txd4_default
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&pinctrl_rxd4_default>;
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};
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/*
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* I2C bus #0 is multi-master environment dedicated for BMC and Bridge IC
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* communication.
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*/
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&i2c0 {
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status = "okay";
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multi-master;
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bus-frequency = <1000000>;
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};
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&i2c1 {
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status = "okay";
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};
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&i2c2 {
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status = "okay";
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i2c-switch@70 {
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compatible = "nxp,pca9548";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x70>;
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i2c-mux-idle-disconnect;
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imux16: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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imux17: i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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imux18: i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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};
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imux19: i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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};
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imux20: i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4>;
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};
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imux21: i2c@5 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <5>;
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};
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imux22: i2c@6 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <6>;
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};
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imux23: i2c@7 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <7>;
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};
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};
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};
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&i2c3 {
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status = "okay";
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};
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&i2c4 {
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status = "okay";
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};
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&i2c5 {
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status = "okay";
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};
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&i2c6 {
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status = "okay";
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};
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&i2c7 {
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status = "okay";
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};
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&i2c8 {
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status = "okay";
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i2c-switch@70 {
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compatible = "nxp,pca9548";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x70>;
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i2c-mux-idle-disconnect;
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imux24: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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imux25: i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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imux26: i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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};
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imux27: i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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};
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imux28: i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4>;
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};
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imux29: i2c@5 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <5>;
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};
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imux30: i2c@6 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <6>;
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};
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imux31: i2c@7 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <7>;
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};
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};
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};
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&i2c9 {
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status = "okay";
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};
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&i2c10 {
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status = "okay";
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};
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&i2c11 {
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status = "okay";
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i2c-switch@76 {
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compatible = "nxp,pca9548";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x76>;
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i2c-mux-idle-disconnect;
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imux32: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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imux33: i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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imux34: i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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};
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imux35: i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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};
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imux36: i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4>;
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};
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imux37: i2c@5 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <5>;
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};
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imux38: i2c@6 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <6>;
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};
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imux39: i2c@7 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <7>;
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};
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};
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};
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&i2c12 {
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status = "okay";
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};
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&i2c13 {
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status = "okay";
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};
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&adc {
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status = "okay";
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};
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&ehci1 {
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status = "okay";
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};
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&uhci {
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status = "okay";
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};
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&sdhci1 {
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/*
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* DMA mode needs to be disabled to avoid conflicts with UHCI
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* Controller in AST2500 SoC.
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*/
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sdhci-caps-mask = <0x0 0x580000>;
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};
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