236 lines
4.1 KiB
Plaintext
236 lines
4.1 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Device Tree file for Armada 385 Allied Telesis x530/GS980MX Board.
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(x530/AT-GS980MX)
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*
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Copyright (C) 2020 Allied Telesis Labs
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*/
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/dts-v1/;
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#include "armada-385.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "x530/AT-GS980MX";
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compatible = "alliedtelesis,gs980mx", "alliedtelesis,x530", "marvell,armada385", "marvell,armada380";
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chosen {
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stdout-path = "serial1:115200n8";
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x40000000>; /* 1GB */
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x3d) 0 0xf4800000 0x80000
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MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
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internal-regs {
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i2c0: i2c@11000 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins>;
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status = "okay";
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};
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uart0: serial@12000 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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};
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};
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};
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&pciec {
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status = "okay";
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};
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&pcie1 {
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status = "okay";
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reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
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reset-delay-us = <400000>;
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};
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&pcie2 {
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status = "okay";
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};
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&devbus_cs1 {
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compatible = "marvell,mvebu-devbus";
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status = "okay";
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devbus,bus-width = <8>;
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devbus,turn-off-ps = <60000>;
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devbus,badr-skew-ps = <0>;
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devbus,acc-first-ps = <124000>;
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devbus,acc-next-ps = <248000>;
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devbus,rd-setup-ps = <0>;
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devbus,rd-hold-ps = <0>;
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/* Write parameters */
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devbus,sync-enable = <0>;
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devbus,wr-high-ps = <60000>;
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devbus,wr-low-ps = <60000>;
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devbus,ale-wr-ps = <60000>;
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nvs@0 {
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status = "okay";
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compatible = "mtd-ram";
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reg = <0 0x00080000>;
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bank-width = <1>;
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label = "nvs";
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};
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};
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&pinctrl {
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i2c0_gpio_pins: i2c-gpio-pins-0 {
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marvell,pins = "mpp2", "mpp3";
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marvell,function = "gpio";
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};
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};
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&i2c0 {
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clock-frequency = <100000>;
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status = "okay";
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-1 = <&i2c0_gpio_pins>;
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scl-gpio = <&gpio0 2 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
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sda-gpio = <&gpio0 3 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
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i2c0mux: mux@71 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nxp,pca9544";
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reg = <0x71>;
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i2c-mux-idle-disconnect;
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i2c@0 { /* POE devices MUX */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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adt7476_2e: hwmon@2e {
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compatible = "adi,adt7476";
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reg = <0x2e>;
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};
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adt7476_2d: hwmon@2d {
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compatible = "adi,adt7476";
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reg = <0x2d>;
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};
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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rtc@68 {
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compatible = "dallas,ds1340";
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reg = <0x68>;
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};
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};
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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gpio@20 {
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compatible = "nxp,pca9554";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x20>;
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};
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};
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};
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};
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&usb0 {
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status = "okay";
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};
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&spi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi1_pins>;
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status = "okay";
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spi-flash@1 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <1>; /* Chip select 1 */
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spi-max-frequency = <54000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@u-boot {
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reg = <0x00000000 0x00100000>;
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label = "u-boot";
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};
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partition@u-boot-env {
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reg = <0x00100000 0x00040000>;
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label = "u-boot-env";
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};
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partition@unused {
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reg = <0x00140000 0x00e80000>;
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label = "unused";
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};
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partition@idprom {
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reg = <0x00fc0000 0x00040000>;
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label = "idprom";
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};
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};
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};
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};
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&nand_controller {
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status = "okay";
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nand@0 {
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reg = <0>;
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label = "pxa3xx_nand-0";
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nand-rb = <0>;
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nand-on-flash-bbt;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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marvell,nand-enable-arbiter;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@user {
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reg = <0x00000000 0x0f000000>;
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label = "user";
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};
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partition@errlog {
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/* Maximum mtdoops size is 8MB, so set to that. */
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reg = <0x0f000000 0x00800000>;
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label = "errlog";
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};
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partition@nand-bbt {
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reg = <0x0f800000 0x00800000>;
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label = "nand-bbt";
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};
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};
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};
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};
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