406 lines
9.8 KiB
C
406 lines
9.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <asm/ptrace.h>
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#include <linux/uaccess.h>
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#include "sfp-util.h"
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#include <math-emu/soft-fp.h>
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#include <math-emu/single.h>
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#include <math-emu/double.h>
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#define OPC_PAL 0x00
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#define OPC_INTA 0x10
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#define OPC_INTL 0x11
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#define OPC_INTS 0x12
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#define OPC_INTM 0x13
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#define OPC_FLTC 0x14
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#define OPC_FLTV 0x15
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#define OPC_FLTI 0x16
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#define OPC_FLTL 0x17
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#define OPC_MISC 0x18
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#define OPC_JSR 0x1a
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#define FOP_SRC_S 0
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#define FOP_SRC_T 2
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#define FOP_SRC_Q 3
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#define FOP_FNC_ADDx 0
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#define FOP_FNC_CVTQL 0
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#define FOP_FNC_SUBx 1
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#define FOP_FNC_MULx 2
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#define FOP_FNC_DIVx 3
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#define FOP_FNC_CMPxUN 4
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#define FOP_FNC_CMPxEQ 5
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#define FOP_FNC_CMPxLT 6
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#define FOP_FNC_CMPxLE 7
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#define FOP_FNC_SQRTx 11
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#define FOP_FNC_CVTxS 12
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#define FOP_FNC_CVTxT 14
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#define FOP_FNC_CVTxQ 15
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#define MISC_TRAPB 0x0000
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#define MISC_EXCB 0x0400
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extern unsigned long alpha_read_fp_reg (unsigned long reg);
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extern void alpha_write_fp_reg (unsigned long reg, unsigned long val);
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extern unsigned long alpha_read_fp_reg_s (unsigned long reg);
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extern void alpha_write_fp_reg_s (unsigned long reg, unsigned long val);
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#ifdef MODULE
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MODULE_DESCRIPTION("FP Software completion module");
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MODULE_LICENSE("GPL v2");
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extern long (*alpha_fp_emul_imprecise)(struct pt_regs *, unsigned long);
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extern long (*alpha_fp_emul) (unsigned long pc);
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static long (*save_emul_imprecise)(struct pt_regs *, unsigned long);
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static long (*save_emul) (unsigned long pc);
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long do_alpha_fp_emul_imprecise(struct pt_regs *, unsigned long);
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long do_alpha_fp_emul(unsigned long);
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static int alpha_fp_emul_init_module(void)
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{
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save_emul_imprecise = alpha_fp_emul_imprecise;
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save_emul = alpha_fp_emul;
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alpha_fp_emul_imprecise = do_alpha_fp_emul_imprecise;
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alpha_fp_emul = do_alpha_fp_emul;
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return 0;
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}
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module_init(alpha_fp_emul_init_module);
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static void alpha_fp_emul_cleanup_module(void)
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{
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alpha_fp_emul_imprecise = save_emul_imprecise;
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alpha_fp_emul = save_emul;
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}
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module_exit(alpha_fp_emul_cleanup_module);
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#undef alpha_fp_emul_imprecise
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#define alpha_fp_emul_imprecise do_alpha_fp_emul_imprecise
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#undef alpha_fp_emul
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#define alpha_fp_emul do_alpha_fp_emul
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#endif /* MODULE */
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/*
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* Emulate the floating point instruction at address PC. Returns -1 if the
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* instruction to be emulated is illegal (such as with the opDEC trap), else
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* the SI_CODE for a SIGFPE signal, else 0 if everything's ok.
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*
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* Notice that the kernel does not and cannot use FP regs. This is good
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* because it means that instead of saving/restoring all fp regs, we simply
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* stick the result of the operation into the appropriate register.
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*/
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long
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alpha_fp_emul (unsigned long pc)
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{
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FP_DECL_EX;
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FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
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FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
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unsigned long fa, fb, fc, func, mode, src;
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unsigned long res, va, vb, vc, swcr, fpcr;
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__u32 insn;
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long si_code;
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get_user(insn, (__u32 __user *)pc);
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fc = (insn >> 0) & 0x1f; /* destination register */
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fb = (insn >> 16) & 0x1f;
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fa = (insn >> 21) & 0x1f;
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func = (insn >> 5) & 0xf;
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src = (insn >> 9) & 0x3;
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mode = (insn >> 11) & 0x3;
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fpcr = rdfpcr();
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swcr = swcr_update_status(current_thread_info()->ieee_state, fpcr);
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if (mode == 3) {
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/* Dynamic -- get rounding mode from fpcr. */
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mode = (fpcr >> FPCR_DYN_SHIFT) & 3;
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}
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switch (src) {
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case FOP_SRC_S:
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va = alpha_read_fp_reg_s(fa);
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vb = alpha_read_fp_reg_s(fb);
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FP_UNPACK_SP(SA, &va);
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FP_UNPACK_SP(SB, &vb);
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switch (func) {
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case FOP_FNC_SUBx:
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FP_SUB_S(SR, SA, SB);
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goto pack_s;
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case FOP_FNC_ADDx:
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FP_ADD_S(SR, SA, SB);
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goto pack_s;
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case FOP_FNC_MULx:
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FP_MUL_S(SR, SA, SB);
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goto pack_s;
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case FOP_FNC_DIVx:
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FP_DIV_S(SR, SA, SB);
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goto pack_s;
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case FOP_FNC_SQRTx:
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FP_SQRT_S(SR, SB);
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goto pack_s;
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}
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goto bad_insn;
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case FOP_SRC_T:
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va = alpha_read_fp_reg(fa);
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vb = alpha_read_fp_reg(fb);
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if ((func & ~3) == FOP_FNC_CMPxUN) {
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FP_UNPACK_RAW_DP(DA, &va);
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FP_UNPACK_RAW_DP(DB, &vb);
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if (!DA_e && !_FP_FRAC_ZEROP_1(DA)) {
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FP_SET_EXCEPTION(FP_EX_DENORM);
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if (FP_DENORM_ZERO)
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_FP_FRAC_SET_1(DA, _FP_ZEROFRAC_1);
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}
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if (!DB_e && !_FP_FRAC_ZEROP_1(DB)) {
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FP_SET_EXCEPTION(FP_EX_DENORM);
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if (FP_DENORM_ZERO)
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_FP_FRAC_SET_1(DB, _FP_ZEROFRAC_1);
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}
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FP_CMP_D(res, DA, DB, 3);
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vc = 0x4000000000000000UL;
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/* CMPTEQ, CMPTUN don't trap on QNaN,
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while CMPTLT and CMPTLE do */
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if (res == 3
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&& ((func & 3) >= 2
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|| FP_ISSIGNAN_D(DA)
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|| FP_ISSIGNAN_D(DB))) {
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FP_SET_EXCEPTION(FP_EX_INVALID);
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}
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switch (func) {
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case FOP_FNC_CMPxUN: if (res != 3) vc = 0; break;
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case FOP_FNC_CMPxEQ: if (res) vc = 0; break;
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case FOP_FNC_CMPxLT: if (res != -1) vc = 0; break;
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case FOP_FNC_CMPxLE: if ((long)res > 0) vc = 0; break;
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}
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goto done_d;
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}
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FP_UNPACK_DP(DA, &va);
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FP_UNPACK_DP(DB, &vb);
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switch (func) {
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case FOP_FNC_SUBx:
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FP_SUB_D(DR, DA, DB);
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goto pack_d;
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case FOP_FNC_ADDx:
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FP_ADD_D(DR, DA, DB);
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goto pack_d;
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case FOP_FNC_MULx:
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FP_MUL_D(DR, DA, DB);
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goto pack_d;
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case FOP_FNC_DIVx:
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FP_DIV_D(DR, DA, DB);
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goto pack_d;
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case FOP_FNC_SQRTx:
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FP_SQRT_D(DR, DB);
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goto pack_d;
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case FOP_FNC_CVTxS:
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/* It is irritating that DEC encoded CVTST with
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SRC == T_floating. It is also interesting that
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the bit used to tell the two apart is /U... */
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if (insn & 0x2000) {
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FP_CONV(S,D,1,1,SR,DB);
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goto pack_s;
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} else {
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vb = alpha_read_fp_reg_s(fb);
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FP_UNPACK_SP(SB, &vb);
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DR_c = DB_c;
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DR_s = DB_s;
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DR_e = DB_e + (1024 - 128);
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DR_f = SB_f << (52 - 23);
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goto pack_d;
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}
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case FOP_FNC_CVTxQ:
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if (DB_c == FP_CLS_NAN
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&& (_FP_FRAC_HIGH_RAW_D(DB) & _FP_QNANBIT_D)) {
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/* AAHB Table B-2 says QNaN should not trigger INV */
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vc = 0;
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} else
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FP_TO_INT_ROUND_D(vc, DB, 64, 2);
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goto done_d;
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}
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goto bad_insn;
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case FOP_SRC_Q:
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vb = alpha_read_fp_reg(fb);
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switch (func) {
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case FOP_FNC_CVTQL:
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/* Notice: We can get here only due to an integer
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overflow. Such overflows are reported as invalid
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ops. We return the result the hw would have
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computed. */
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vc = ((vb & 0xc0000000) << 32 | /* sign and msb */
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(vb & 0x3fffffff) << 29); /* rest of the int */
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FP_SET_EXCEPTION (FP_EX_INVALID);
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goto done_d;
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case FOP_FNC_CVTxS:
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FP_FROM_INT_S(SR, ((long)vb), 64, long);
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goto pack_s;
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case FOP_FNC_CVTxT:
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FP_FROM_INT_D(DR, ((long)vb), 64, long);
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goto pack_d;
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}
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goto bad_insn;
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}
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goto bad_insn;
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pack_s:
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FP_PACK_SP(&vc, SR);
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if ((_fex & FP_EX_UNDERFLOW) && (swcr & IEEE_MAP_UMZ))
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vc = 0;
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alpha_write_fp_reg_s(fc, vc);
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goto done;
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pack_d:
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FP_PACK_DP(&vc, DR);
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if ((_fex & FP_EX_UNDERFLOW) && (swcr & IEEE_MAP_UMZ))
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vc = 0;
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done_d:
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alpha_write_fp_reg(fc, vc);
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goto done;
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/*
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* Take the appropriate action for each possible
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* floating-point result:
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*
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* - Set the appropriate bits in the FPCR
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* - If the specified exception is enabled in the FPCR,
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* return. The caller (entArith) will dispatch
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* the appropriate signal to the translated program.
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*
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* In addition, properly track the exception state in software
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* as described in the Alpha Architecture Handbook section 4.7.7.3.
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*/
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done:
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if (_fex) {
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/* Record exceptions in software control word. */
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swcr |= (_fex << IEEE_STATUS_TO_EXCSUM_SHIFT);
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current_thread_info()->ieee_state
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|= (_fex << IEEE_STATUS_TO_EXCSUM_SHIFT);
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/* Update hardware control register. */
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fpcr &= (~FPCR_MASK | FPCR_DYN_MASK);
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fpcr |= ieee_swcr_to_fpcr(swcr);
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wrfpcr(fpcr);
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/* Do we generate a signal? */
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_fex = _fex & swcr & IEEE_TRAP_ENABLE_MASK;
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si_code = 0;
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if (_fex) {
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if (_fex & IEEE_TRAP_ENABLE_DNO) si_code = FPE_FLTUND;
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if (_fex & IEEE_TRAP_ENABLE_INE) si_code = FPE_FLTRES;
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if (_fex & IEEE_TRAP_ENABLE_UNF) si_code = FPE_FLTUND;
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if (_fex & IEEE_TRAP_ENABLE_OVF) si_code = FPE_FLTOVF;
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if (_fex & IEEE_TRAP_ENABLE_DZE) si_code = FPE_FLTDIV;
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if (_fex & IEEE_TRAP_ENABLE_INV) si_code = FPE_FLTINV;
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}
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return si_code;
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}
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/* We used to write the destination register here, but DEC FORTRAN
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requires that the result *always* be written... so we do the write
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immediately after the operations above. */
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return 0;
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bad_insn:
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printk(KERN_ERR "alpha_fp_emul: Invalid FP insn %#x at %#lx\n",
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insn, pc);
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return -1;
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}
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long
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alpha_fp_emul_imprecise (struct pt_regs *regs, unsigned long write_mask)
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{
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unsigned long trigger_pc = regs->pc - 4;
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unsigned long insn, opcode, rc, si_code = 0;
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/*
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* Turn off the bits corresponding to registers that are the
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* target of instructions that set bits in the exception
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* summary register. We have some slack doing this because a
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* register that is the target of a trapping instruction can
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* be written at most once in the trap shadow.
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*
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* Branches, jumps, TRAPBs, EXCBs and calls to PALcode all
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* bound the trap shadow, so we need not look any further than
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* up to the first occurrence of such an instruction.
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*/
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while (write_mask) {
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get_user(insn, (__u32 __user *)(trigger_pc));
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opcode = insn >> 26;
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rc = insn & 0x1f;
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switch (opcode) {
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case OPC_PAL:
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case OPC_JSR:
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case 0x30 ... 0x3f: /* branches */
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goto egress;
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case OPC_MISC:
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switch (insn & 0xffff) {
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case MISC_TRAPB:
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case MISC_EXCB:
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goto egress;
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default:
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break;
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}
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break;
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case OPC_INTA:
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case OPC_INTL:
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case OPC_INTS:
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case OPC_INTM:
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write_mask &= ~(1UL << rc);
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break;
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case OPC_FLTC:
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case OPC_FLTV:
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case OPC_FLTI:
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case OPC_FLTL:
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write_mask &= ~(1UL << (rc + 32));
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break;
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}
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if (!write_mask) {
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/* Re-execute insns in the trap-shadow. */
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regs->pc = trigger_pc + 4;
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si_code = alpha_fp_emul(trigger_pc);
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goto egress;
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}
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trigger_pc -= 4;
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}
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egress:
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return si_code;
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}
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