170 lines
7.6 KiB
ReStructuredText
170 lines
7.6 KiB
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==============================
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Memory Layout on AArch64 Linux
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==============================
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Author: Catalin Marinas <catalin.marinas@arm.com>
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This document describes the virtual memory layout used by the AArch64
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Linux kernel. The architecture allows up to 4 levels of translation
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tables with a 4KB page size and up to 3 levels with a 64KB page size.
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AArch64 Linux uses either 3 levels or 4 levels of translation tables
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with the 4KB page configuration, allowing 39-bit (512GB) or 48-bit
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(256TB) virtual addresses, respectively, for both user and kernel. With
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64KB pages, only 2 levels of translation tables, allowing 42-bit (4TB)
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virtual address, are used but the memory layout is the same.
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ARMv8.2 adds optional support for Large Virtual Address space. This is
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only available when running with a 64KB page size and expands the
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number of descriptors in the first level of translation.
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User addresses have bits 63:48 set to 0 while the kernel addresses have
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the same bits set to 1. TTBRx selection is given by bit 63 of the
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virtual address. The swapper_pg_dir contains only kernel (global)
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mappings while the user pgd contains only user (non-global) mappings.
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The swapper_pg_dir address is written to TTBR1 and never written to
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TTBR0.
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AArch64 Linux memory layout with 4KB pages + 4 levels (48-bit)::
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Start End Size Use
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-----------------------------------------------------------------------
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0000000000000000 0000ffffffffffff 256TB user
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ffff000000000000 ffff7fffffffffff 128TB kernel logical memory map
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[ffff600000000000 ffff7fffffffffff] 32TB [kasan shadow region]
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ffff800000000000 ffff800007ffffff 128MB bpf jit region
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ffff800008000000 ffff80000fffffff 128MB modules
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ffff800010000000 fffffbffefffffff 124TB vmalloc
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fffffbfff0000000 fffffbfffdffffff 224MB fixed mappings (top down)
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fffffbfffe000000 fffffbfffe7fffff 8MB [guard region]
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fffffbfffe800000 fffffbffff7fffff 16MB PCI I/O space
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fffffbffff800000 fffffbffffffffff 8MB [guard region]
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fffffc0000000000 fffffdffffffffff 2TB vmemmap
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fffffe0000000000 ffffffffffffffff 2TB [guard region]
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AArch64 Linux memory layout with 64KB pages + 3 levels (52-bit with HW support)::
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Start End Size Use
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-----------------------------------------------------------------------
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0000000000000000 000fffffffffffff 4PB user
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fff0000000000000 ffff7fffffffffff ~4PB kernel logical memory map
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[fffd800000000000 ffff7fffffffffff] 512TB [kasan shadow region]
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ffff800000000000 ffff800007ffffff 128MB bpf jit region
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ffff800008000000 ffff80000fffffff 128MB modules
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ffff800010000000 fffffbffefffffff 124TB vmalloc
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fffffbfff0000000 fffffbfffdffffff 224MB fixed mappings (top down)
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fffffbfffe000000 fffffbfffe7fffff 8MB [guard region]
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fffffbfffe800000 fffffbffff7fffff 16MB PCI I/O space
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fffffbffff800000 fffffbffffffffff 8MB [guard region]
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fffffc0000000000 ffffffdfffffffff ~4TB vmemmap
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ffffffe000000000 ffffffffffffffff 128GB [guard region]
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Translation table lookup with 4KB pages::
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+--------+--------+--------+--------+--------+--------+--------+--------+
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|63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
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+--------+--------+--------+--------+--------+--------+--------+--------+
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| | | | | |
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| | | | | v
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| | | | | [11:0] in-page offset
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| | | | +-> [20:12] L3 index
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| | | +-----------> [29:21] L2 index
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| | +---------------------> [38:30] L1 index
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| +-------------------------------> [47:39] L0 index
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+-------------------------------------------------> [63] TTBR0/1
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Translation table lookup with 64KB pages::
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+--------+--------+--------+--------+--------+--------+--------+--------+
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|63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
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+--------+--------+--------+--------+--------+--------+--------+--------+
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| | | | |
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| | | | v
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| | | | [15:0] in-page offset
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| | | +----------> [28:16] L3 index
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| | +--------------------------> [41:29] L2 index
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| +-------------------------------> [47:42] L1 index (48-bit)
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| [51:42] L1 index (52-bit)
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+-------------------------------------------------> [63] TTBR0/1
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When using KVM without the Virtualization Host Extensions, the
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hypervisor maps kernel pages in EL2 at a fixed (and potentially
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random) offset from the linear mapping. See the kern_hyp_va macro and
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kvm_update_va_mask function for more details. MMIO devices such as
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GICv2 gets mapped next to the HYP idmap page, as do vectors when
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ARM64_SPECTRE_V3A is enabled for particular CPUs.
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When using KVM with the Virtualization Host Extensions, no additional
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mappings are created, since the host kernel runs directly in EL2.
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52-bit VA support in the kernel
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-------------------------------
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If the ARMv8.2-LVA optional feature is present, and we are running
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with a 64KB page size; then it is possible to use 52-bits of address
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space for both userspace and kernel addresses. However, any kernel
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binary that supports 52-bit must also be able to fall back to 48-bit
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at early boot time if the hardware feature is not present.
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This fallback mechanism necessitates the kernel .text to be in the
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higher addresses such that they are invariant to 48/52-bit VAs. Due
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to the kasan shadow being a fraction of the entire kernel VA space,
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the end of the kasan shadow must also be in the higher half of the
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kernel VA space for both 48/52-bit. (Switching from 48-bit to 52-bit,
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the end of the kasan shadow is invariant and dependent on ~0UL,
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whilst the start address will "grow" towards the lower addresses).
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In order to optimise phys_to_virt and virt_to_phys, the PAGE_OFFSET
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is kept constant at 0xFFF0000000000000 (corresponding to 52-bit),
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this obviates the need for an extra variable read. The physvirt
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offset and vmemmap offsets are computed at early boot to enable
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this logic.
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As a single binary will need to support both 48-bit and 52-bit VA
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spaces, the VMEMMAP must be sized large enough for 52-bit VAs and
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also must be sized large enough to accommodate a fixed PAGE_OFFSET.
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Most code in the kernel should not need to consider the VA_BITS, for
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code that does need to know the VA size the variables are
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defined as follows:
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VA_BITS constant the *maximum* VA space size
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VA_BITS_MIN constant the *minimum* VA space size
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vabits_actual variable the *actual* VA space size
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Maximum and minimum sizes can be useful to ensure that buffers are
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sized large enough or that addresses are positioned close enough for
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the "worst" case.
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52-bit userspace VAs
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--------------------
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To maintain compatibility with software that relies on the ARMv8.0
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VA space maximum size of 48-bits, the kernel will, by default,
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return virtual addresses to userspace from a 48-bit range.
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Software can "opt-in" to receiving VAs from a 52-bit space by
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specifying an mmap hint parameter that is larger than 48-bit.
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For example:
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.. code-block:: c
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maybe_high_address = mmap(~0UL, size, prot, flags,...);
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It is also possible to build a debug kernel that returns addresses
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from a 52-bit space by enabling the following kernel config options:
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.. code-block:: sh
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CONFIG_EXPERT=y && CONFIG_ARM64_FORCE_52BIT=y
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Note that this option is only intended for debugging applications
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and should not be used in production.
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