143 lines
3.6 KiB
C
143 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* RISC-V performance counter support.
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*
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* Copyright (C) 2021 Western Digital Corporation or its affiliates.
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*
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* This implementation is based on old RISC-V perf and ARM perf event code
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* which are in turn based on sparc64 and x86 code.
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*/
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#include <linux/mod_devicetable.h>
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#include <linux/perf/riscv_pmu.h>
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#include <linux/platform_device.h>
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#define RISCV_PMU_LEGACY_CYCLE 0
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#define RISCV_PMU_LEGACY_INSTRET 1
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#define RISCV_PMU_LEGACY_NUM_CTR 2
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static bool pmu_init_done;
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static int pmu_legacy_ctr_get_idx(struct perf_event *event)
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{
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struct perf_event_attr *attr = &event->attr;
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if (event->attr.type != PERF_TYPE_HARDWARE)
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return -EOPNOTSUPP;
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if (attr->config == PERF_COUNT_HW_CPU_CYCLES)
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return RISCV_PMU_LEGACY_CYCLE;
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else if (attr->config == PERF_COUNT_HW_INSTRUCTIONS)
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return RISCV_PMU_LEGACY_INSTRET;
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else
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return -EOPNOTSUPP;
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}
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/* For legacy config & counter index are same */
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static int pmu_legacy_event_map(struct perf_event *event, u64 *config)
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{
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return pmu_legacy_ctr_get_idx(event);
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}
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static u64 pmu_legacy_read_ctr(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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u64 val;
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if (idx == RISCV_PMU_LEGACY_CYCLE) {
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val = riscv_pmu_ctr_read_csr(CSR_CYCLE);
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if (IS_ENABLED(CONFIG_32BIT))
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val = (u64)riscv_pmu_ctr_read_csr(CSR_CYCLEH) << 32 | val;
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} else if (idx == RISCV_PMU_LEGACY_INSTRET) {
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val = riscv_pmu_ctr_read_csr(CSR_INSTRET);
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if (IS_ENABLED(CONFIG_32BIT))
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val = ((u64)riscv_pmu_ctr_read_csr(CSR_INSTRETH)) << 32 | val;
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} else
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return 0;
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return val;
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}
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static void pmu_legacy_ctr_start(struct perf_event *event, u64 ival)
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{
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struct hw_perf_event *hwc = &event->hw;
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u64 initial_val = pmu_legacy_read_ctr(event);
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/**
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* The legacy method doesn't really have a start/stop method.
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* It also can not update the counter with a initial value.
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* But we still need to set the prev_count so that read() can compute
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* the delta. Just use the current counter value to set the prev_count.
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*/
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local64_set(&hwc->prev_count, initial_val);
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}
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/**
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* This is just a simple implementation to allow legacy implementations
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* compatible with new RISC-V PMU driver framework.
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* This driver only allows reading two counters i.e CYCLE & INSTRET.
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* However, it can not start or stop the counter. Thus, it is not very useful
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* will be removed in future.
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*/
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static void pmu_legacy_init(struct riscv_pmu *pmu)
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{
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pr_info("Legacy PMU implementation is available\n");
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pmu->num_counters = RISCV_PMU_LEGACY_NUM_CTR;
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pmu->ctr_start = pmu_legacy_ctr_start;
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pmu->ctr_stop = NULL;
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pmu->event_map = pmu_legacy_event_map;
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pmu->ctr_get_idx = pmu_legacy_ctr_get_idx;
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pmu->ctr_get_width = NULL;
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pmu->ctr_clear_idx = NULL;
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pmu->ctr_read = pmu_legacy_read_ctr;
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perf_pmu_register(&pmu->pmu, "cpu", PERF_TYPE_RAW);
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}
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static int pmu_legacy_device_probe(struct platform_device *pdev)
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{
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struct riscv_pmu *pmu = NULL;
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pmu = riscv_pmu_alloc();
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if (!pmu)
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return -ENOMEM;
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pmu_legacy_init(pmu);
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return 0;
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}
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static struct platform_driver pmu_legacy_driver = {
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.probe = pmu_legacy_device_probe,
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.driver = {
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.name = RISCV_PMU_LEGACY_PDEV_NAME,
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},
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};
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static int __init riscv_pmu_legacy_devinit(void)
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{
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int ret;
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struct platform_device *pdev;
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if (likely(pmu_init_done))
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return 0;
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ret = platform_driver_register(&pmu_legacy_driver);
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if (ret)
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return ret;
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pdev = platform_device_register_simple(RISCV_PMU_LEGACY_PDEV_NAME, -1, NULL, 0);
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if (IS_ERR(pdev)) {
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platform_driver_unregister(&pmu_legacy_driver);
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return PTR_ERR(pdev);
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}
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return ret;
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}
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late_initcall(riscv_pmu_legacy_devinit);
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void riscv_pmu_legacy_skip_init(void)
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{
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pmu_init_done = true;
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}
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