348 lines
9.2 KiB
C
348 lines
9.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Marvell EBU SoC Device Bus Controller
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* (memory controller for NOR/NAND/SRAM/FPGA devices)
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*
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* Copyright (C) 2013-2014 Marvell
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/mbus.h>
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#include <linux/of_platform.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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/* Register definitions */
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#define ARMADA_DEV_WIDTH_SHIFT 30
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#define ARMADA_BADR_SKEW_SHIFT 28
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#define ARMADA_RD_HOLD_SHIFT 23
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#define ARMADA_ACC_NEXT_SHIFT 17
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#define ARMADA_RD_SETUP_SHIFT 12
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#define ARMADA_ACC_FIRST_SHIFT 6
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#define ARMADA_SYNC_ENABLE_SHIFT 24
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#define ARMADA_WR_HIGH_SHIFT 16
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#define ARMADA_WR_LOW_SHIFT 8
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#define ARMADA_READ_PARAM_OFFSET 0x0
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#define ARMADA_WRITE_PARAM_OFFSET 0x4
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#define ORION_RESERVED (0x2 << 30)
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#define ORION_BADR_SKEW_SHIFT 28
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#define ORION_WR_HIGH_EXT_BIT BIT(27)
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#define ORION_WR_HIGH_EXT_MASK 0x8
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#define ORION_WR_LOW_EXT_BIT BIT(26)
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#define ORION_WR_LOW_EXT_MASK 0x8
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#define ORION_ALE_WR_EXT_BIT BIT(25)
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#define ORION_ALE_WR_EXT_MASK 0x8
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#define ORION_ACC_NEXT_EXT_BIT BIT(24)
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#define ORION_ACC_NEXT_EXT_MASK 0x10
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#define ORION_ACC_FIRST_EXT_BIT BIT(23)
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#define ORION_ACC_FIRST_EXT_MASK 0x10
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#define ORION_TURN_OFF_EXT_BIT BIT(22)
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#define ORION_TURN_OFF_EXT_MASK 0x8
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#define ORION_DEV_WIDTH_SHIFT 20
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#define ORION_WR_HIGH_SHIFT 17
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#define ORION_WR_HIGH_MASK 0x7
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#define ORION_WR_LOW_SHIFT 14
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#define ORION_WR_LOW_MASK 0x7
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#define ORION_ALE_WR_SHIFT 11
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#define ORION_ALE_WR_MASK 0x7
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#define ORION_ACC_NEXT_SHIFT 7
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#define ORION_ACC_NEXT_MASK 0xF
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#define ORION_ACC_FIRST_SHIFT 3
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#define ORION_ACC_FIRST_MASK 0xF
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#define ORION_TURN_OFF_SHIFT 0
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#define ORION_TURN_OFF_MASK 0x7
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struct devbus_read_params {
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u32 bus_width;
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u32 badr_skew;
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u32 turn_off;
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u32 acc_first;
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u32 acc_next;
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u32 rd_setup;
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u32 rd_hold;
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};
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struct devbus_write_params {
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u32 sync_enable;
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u32 wr_high;
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u32 wr_low;
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u32 ale_wr;
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};
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struct devbus {
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struct device *dev;
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void __iomem *base;
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unsigned long tick_ps;
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};
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static int get_timing_param_ps(struct devbus *devbus,
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struct device_node *node,
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const char *name,
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u32 *ticks)
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{
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u32 time_ps;
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int err;
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err = of_property_read_u32(node, name, &time_ps);
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if (err < 0) {
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dev_err(devbus->dev, "%pOF has no '%s' property\n",
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node, name);
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return err;
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}
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*ticks = (time_ps + devbus->tick_ps - 1) / devbus->tick_ps;
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dev_dbg(devbus->dev, "%s: %u ps -> 0x%x\n",
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name, time_ps, *ticks);
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return 0;
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}
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static int devbus_get_timing_params(struct devbus *devbus,
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struct device_node *node,
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struct devbus_read_params *r,
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struct devbus_write_params *w)
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{
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int err;
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err = of_property_read_u32(node, "devbus,bus-width", &r->bus_width);
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if (err < 0) {
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dev_err(devbus->dev,
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"%pOF has no 'devbus,bus-width' property\n",
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node);
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return err;
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}
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/*
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* The bus width is encoded into the register as 0 for 8 bits,
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* and 1 for 16 bits, so we do the necessary conversion here.
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*/
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if (r->bus_width == 8) {
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r->bus_width = 0;
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} else if (r->bus_width == 16) {
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r->bus_width = 1;
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} else {
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dev_err(devbus->dev, "invalid bus width %d\n", r->bus_width);
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return -EINVAL;
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}
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err = get_timing_param_ps(devbus, node, "devbus,badr-skew-ps",
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&r->badr_skew);
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if (err < 0)
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return err;
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err = get_timing_param_ps(devbus, node, "devbus,turn-off-ps",
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&r->turn_off);
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if (err < 0)
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return err;
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err = get_timing_param_ps(devbus, node, "devbus,acc-first-ps",
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&r->acc_first);
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if (err < 0)
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return err;
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err = get_timing_param_ps(devbus, node, "devbus,acc-next-ps",
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&r->acc_next);
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if (err < 0)
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return err;
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if (of_device_is_compatible(devbus->dev->of_node, "marvell,mvebu-devbus")) {
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err = get_timing_param_ps(devbus, node, "devbus,rd-setup-ps",
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&r->rd_setup);
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if (err < 0)
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return err;
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err = get_timing_param_ps(devbus, node, "devbus,rd-hold-ps",
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&r->rd_hold);
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if (err < 0)
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return err;
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err = of_property_read_u32(node, "devbus,sync-enable",
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&w->sync_enable);
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if (err < 0) {
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dev_err(devbus->dev,
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"%pOF has no 'devbus,sync-enable' property\n",
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node);
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return err;
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}
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}
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err = get_timing_param_ps(devbus, node, "devbus,ale-wr-ps",
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&w->ale_wr);
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if (err < 0)
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return err;
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err = get_timing_param_ps(devbus, node, "devbus,wr-low-ps",
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&w->wr_low);
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if (err < 0)
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return err;
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err = get_timing_param_ps(devbus, node, "devbus,wr-high-ps",
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&w->wr_high);
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if (err < 0)
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return err;
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return 0;
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}
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static void devbus_orion_set_timing_params(struct devbus *devbus,
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struct device_node *node,
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struct devbus_read_params *r,
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struct devbus_write_params *w)
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{
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u32 value;
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/*
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* The hardware designers found it would be a good idea to
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* split most of the values in the register into two fields:
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* one containing all the low-order bits, and another one
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* containing just the high-order bit. For all of those
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* fields, we have to split the value into these two parts.
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*/
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value = (r->turn_off & ORION_TURN_OFF_MASK) << ORION_TURN_OFF_SHIFT |
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(r->acc_first & ORION_ACC_FIRST_MASK) << ORION_ACC_FIRST_SHIFT |
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(r->acc_next & ORION_ACC_NEXT_MASK) << ORION_ACC_NEXT_SHIFT |
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(w->ale_wr & ORION_ALE_WR_MASK) << ORION_ALE_WR_SHIFT |
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(w->wr_low & ORION_WR_LOW_MASK) << ORION_WR_LOW_SHIFT |
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(w->wr_high & ORION_WR_HIGH_MASK) << ORION_WR_HIGH_SHIFT |
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r->bus_width << ORION_DEV_WIDTH_SHIFT |
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((r->turn_off & ORION_TURN_OFF_EXT_MASK) ? ORION_TURN_OFF_EXT_BIT : 0) |
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((r->acc_first & ORION_ACC_FIRST_EXT_MASK) ? ORION_ACC_FIRST_EXT_BIT : 0) |
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((r->acc_next & ORION_ACC_NEXT_EXT_MASK) ? ORION_ACC_NEXT_EXT_BIT : 0) |
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((w->ale_wr & ORION_ALE_WR_EXT_MASK) ? ORION_ALE_WR_EXT_BIT : 0) |
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((w->wr_low & ORION_WR_LOW_EXT_MASK) ? ORION_WR_LOW_EXT_BIT : 0) |
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((w->wr_high & ORION_WR_HIGH_EXT_MASK) ? ORION_WR_HIGH_EXT_BIT : 0) |
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(r->badr_skew << ORION_BADR_SKEW_SHIFT) |
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ORION_RESERVED;
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writel(value, devbus->base);
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}
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static void devbus_armada_set_timing_params(struct devbus *devbus,
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struct device_node *node,
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struct devbus_read_params *r,
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struct devbus_write_params *w)
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{
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u32 value;
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/* Set read timings */
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value = r->bus_width << ARMADA_DEV_WIDTH_SHIFT |
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r->badr_skew << ARMADA_BADR_SKEW_SHIFT |
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r->rd_hold << ARMADA_RD_HOLD_SHIFT |
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r->acc_next << ARMADA_ACC_NEXT_SHIFT |
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r->rd_setup << ARMADA_RD_SETUP_SHIFT |
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r->acc_first << ARMADA_ACC_FIRST_SHIFT |
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r->turn_off;
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dev_dbg(devbus->dev, "read parameters register 0x%p = 0x%x\n",
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devbus->base + ARMADA_READ_PARAM_OFFSET,
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value);
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writel(value, devbus->base + ARMADA_READ_PARAM_OFFSET);
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/* Set write timings */
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value = w->sync_enable << ARMADA_SYNC_ENABLE_SHIFT |
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w->wr_low << ARMADA_WR_LOW_SHIFT |
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w->wr_high << ARMADA_WR_HIGH_SHIFT |
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w->ale_wr;
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dev_dbg(devbus->dev, "write parameters register: 0x%p = 0x%x\n",
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devbus->base + ARMADA_WRITE_PARAM_OFFSET,
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value);
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writel(value, devbus->base + ARMADA_WRITE_PARAM_OFFSET);
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}
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static int mvebu_devbus_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *node = pdev->dev.of_node;
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struct devbus_read_params r;
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struct devbus_write_params w;
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struct devbus *devbus;
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struct clk *clk;
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unsigned long rate;
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int err;
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devbus = devm_kzalloc(&pdev->dev, sizeof(struct devbus), GFP_KERNEL);
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if (!devbus)
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return -ENOMEM;
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devbus->dev = dev;
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devbus->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(devbus->base))
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return PTR_ERR(devbus->base);
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clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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clk_prepare_enable(clk);
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/*
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* Obtain clock period in picoseconds,
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* we need this in order to convert timing
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* parameters from cycles to picoseconds.
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*/
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rate = clk_get_rate(clk) / 1000;
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devbus->tick_ps = 1000000000 / rate;
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dev_dbg(devbus->dev, "Setting timing parameter, tick is %lu ps\n",
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devbus->tick_ps);
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if (!of_property_read_bool(node, "devbus,keep-config")) {
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/* Read the Device Tree node */
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err = devbus_get_timing_params(devbus, node, &r, &w);
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if (err < 0)
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return err;
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/* Set the new timing parameters */
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if (of_device_is_compatible(node, "marvell,orion-devbus"))
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devbus_orion_set_timing_params(devbus, node, &r, &w);
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else
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devbus_armada_set_timing_params(devbus, node, &r, &w);
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}
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/*
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* We need to create a child device explicitly from here to
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* guarantee that the child will be probed after the timing
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* parameters for the bus are written.
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*/
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err = of_platform_populate(node, NULL, NULL, dev);
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if (err < 0)
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return err;
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return 0;
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}
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static const struct of_device_id mvebu_devbus_of_match[] = {
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{ .compatible = "marvell,mvebu-devbus" },
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{ .compatible = "marvell,orion-devbus" },
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{},
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};
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MODULE_DEVICE_TABLE(of, mvebu_devbus_of_match);
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static struct platform_driver mvebu_devbus_driver = {
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.probe = mvebu_devbus_probe,
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.driver = {
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.name = "mvebu-devbus",
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.of_match_table = mvebu_devbus_of_match,
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},
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};
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static int __init mvebu_devbus_init(void)
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{
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return platform_driver_register(&mvebu_devbus_driver);
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}
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module_init(mvebu_devbus_init);
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Ezequiel Garcia <ezequiel.garcia@free-electrons.com>");
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MODULE_DESCRIPTION("Marvell EBU SoC Device Bus controller");
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