274 lines
6.0 KiB
C
274 lines
6.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* linux/arch/powerpc/platforms/cell/cell_setup.c
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*
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* Copyright (C) 1995 Linus Torvalds
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* Adapted from 'alpha' version by Gary Thomas
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* Modified by Cort Dougan (cort@cs.nmt.edu)
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* Modified by PPC64 Team, IBM Corp
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* Modified by Cell Team, IBM Deutschland Entwicklung GmbH
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*/
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#undef DEBUG
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/stddef.h>
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#include <linux/export.h>
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#include <linux/unistd.h>
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#include <linux/user.h>
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#include <linux/reboot.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/seq_file.h>
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#include <linux/root_dev.h>
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#include <linux/console.h>
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#include <linux/mutex.h>
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#include <linux/memory_hotplug.h>
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#include <linux/of_platform.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/rtas.h>
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#include <asm/pci-bridge.h>
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#include <asm/iommu.h>
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#include <asm/dma.h>
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#include <asm/machdep.h>
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#include <asm/time.h>
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#include <asm/nvram.h>
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#include <asm/cputable.h>
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#include <asm/ppc-pci.h>
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#include <asm/irq.h>
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#include <asm/spu.h>
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#include <asm/spu_priv1.h>
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#include <asm/udbg.h>
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#include <asm/mpic.h>
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#include <asm/cell-regs.h>
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#include <asm/io-workarounds.h>
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#include "cell.h"
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#include "interrupt.h"
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#include "pervasive.h"
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#include "ras.h"
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#ifdef DEBUG
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#define DBG(fmt...) udbg_printf(fmt)
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#else
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#define DBG(fmt...)
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#endif
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static void cell_show_cpuinfo(struct seq_file *m)
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{
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struct device_node *root;
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const char *model = "";
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root = of_find_node_by_path("/");
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if (root)
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model = of_get_property(root, "model", NULL);
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seq_printf(m, "machine\t\t: CHRP %s\n", model);
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of_node_put(root);
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}
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static void cell_progress(char *s, unsigned short hex)
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{
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printk("*** %04x : %s\n", hex, s ? s : "");
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}
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static void cell_fixup_pcie_rootcomplex(struct pci_dev *dev)
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{
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struct pci_controller *hose;
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const char *s;
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int i;
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if (!machine_is(cell))
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return;
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/* We're searching for a direct child of the PHB */
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if (dev->bus->self != NULL || dev->devfn != 0)
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return;
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hose = pci_bus_to_host(dev->bus);
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if (hose == NULL)
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return;
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/* Only on PCIE */
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if (!of_device_is_compatible(hose->dn, "pciex"))
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return;
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/* And only on axon */
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s = of_get_property(hose->dn, "model", NULL);
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if (!s || strcmp(s, "Axon") != 0)
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return;
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for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
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dev->resource[i].start = dev->resource[i].end = 0;
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dev->resource[i].flags = 0;
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}
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printk(KERN_DEBUG "PCI: Hiding resources on Axon PCIE RC %s\n",
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pci_name(dev));
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, cell_fixup_pcie_rootcomplex);
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static int cell_setup_phb(struct pci_controller *phb)
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{
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const char *model;
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struct device_node *np;
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int rc = rtas_setup_phb(phb);
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if (rc)
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return rc;
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phb->controller_ops = cell_pci_controller_ops;
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np = phb->dn;
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model = of_get_property(np, "model", NULL);
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if (model == NULL || !of_node_name_eq(np, "pci"))
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return 0;
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/* Setup workarounds for spider */
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if (strcmp(model, "Spider"))
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return 0;
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iowa_register_bus(phb, &spiderpci_ops, &spiderpci_iowa_init,
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(void *)SPIDER_PCI_REG_BASE);
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return 0;
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}
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static const struct of_device_id cell_bus_ids[] __initconst = {
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{ .type = "soc", },
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{ .compatible = "soc", },
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{ .type = "spider", },
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{ .type = "axon", },
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{ .type = "plb5", },
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{ .type = "plb4", },
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{ .type = "opb", },
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{ .type = "ebc", },
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{},
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};
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static int __init cell_publish_devices(void)
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{
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struct device_node *root = of_find_node_by_path("/");
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struct device_node *np;
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int node;
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/* Publish OF platform devices for southbridge IOs */
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of_platform_bus_probe(NULL, cell_bus_ids, NULL);
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/* On spider based blades, we need to manually create the OF
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* platform devices for the PCI host bridges
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*/
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for_each_child_of_node(root, np) {
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if (!of_node_is_type(np, "pci") && !of_node_is_type(np, "pciex"))
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continue;
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of_platform_device_create(np, NULL, NULL);
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}
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/* There is no device for the MIC memory controller, thus we create
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* a platform device for it to attach the EDAC driver to.
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*/
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for_each_online_node(node) {
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if (cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(node)) == NULL)
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continue;
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platform_device_register_simple("cbe-mic", node, NULL, 0);
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}
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return 0;
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}
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machine_subsys_initcall(cell, cell_publish_devices);
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static void __init mpic_init_IRQ(void)
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{
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struct device_node *dn;
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struct mpic *mpic;
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for_each_node_by_name(dn, "interrupt-controller") {
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if (!of_device_is_compatible(dn, "CBEA,platform-open-pic"))
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continue;
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/* The MPIC driver will get everything it needs from the
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* device-tree, just pass 0 to all arguments
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*/
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mpic = mpic_alloc(dn, 0, MPIC_SECONDARY | MPIC_NO_RESET,
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0, 0, " MPIC ");
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if (mpic == NULL)
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continue;
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mpic_init(mpic);
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}
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}
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static void __init cell_init_irq(void)
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{
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iic_init_IRQ();
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spider_init_IRQ();
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mpic_init_IRQ();
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}
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static void __init cell_set_dabrx(void)
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{
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mtspr(SPRN_DABRX, DABRX_KERNEL | DABRX_USER);
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}
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static void __init cell_setup_arch(void)
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{
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#ifdef CONFIG_SPU_BASE
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spu_priv1_ops = &spu_priv1_mmio_ops;
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spu_management_ops = &spu_management_of_ops;
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#endif
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cbe_regs_init();
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cell_set_dabrx();
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#ifdef CONFIG_CBE_RAS
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cbe_ras_init();
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#endif
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#ifdef CONFIG_SMP
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smp_init_cell();
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#endif
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/* init to some ~sane value until calibrate_delay() runs */
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loops_per_jiffy = 50000000;
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/* Find and initialize PCI host bridges */
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init_pci_config_tokens();
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cbe_pervasive_init();
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mmio_nvram_init();
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}
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static int __init cell_probe(void)
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{
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if (!of_machine_is_compatible("IBM,CBEA") &&
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!of_machine_is_compatible("IBM,CPBW-1.0"))
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return 0;
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pm_power_off = rtas_power_off;
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return 1;
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}
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define_machine(cell) {
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.name = "Cell",
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.probe = cell_probe,
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.setup_arch = cell_setup_arch,
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.show_cpuinfo = cell_show_cpuinfo,
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.restart = rtas_restart,
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.halt = rtas_halt,
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.get_boot_time = rtas_get_boot_time,
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.get_rtc_time = rtas_get_rtc_time,
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.set_rtc_time = rtas_set_rtc_time,
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.calibrate_decr = generic_calibrate_decr,
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.progress = cell_progress,
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.init_IRQ = cell_init_irq,
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.pci_setup_phb = cell_setup_phb,
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};
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struct pci_controller_ops cell_pci_controller_ops;
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