839 lines
22 KiB
C
839 lines
22 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Parisc performance counters
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* Copyright (C) 2001 Randolph Chung <tausq@debian.org>
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*
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* This code is derived, with permission, from HP/UX sources.
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*/
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/*
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* Edited comment from original sources:
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*
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* This driver programs the PCX-U/PCX-W performance counters
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* on the PA-RISC 2.0 chips. The driver keeps all images now
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* internally to the kernel to hopefully eliminate the possibility
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* of a bad image halting the CPU. Also, there are different
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* images for the PCX-W and later chips vs the PCX-U chips.
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*
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* Only 1 process is allowed to access the driver at any time,
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* so the only protection that is needed is at open and close.
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* A variable "perf_enabled" is used to hold the state of the
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* driver. The spinlock "perf_lock" is used to protect the
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* modification of the state during open/close operations so
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* multiple processes don't get into the driver simultaneously.
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*
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* This driver accesses the processor directly vs going through
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* the PDC INTRIGUE calls. This is done to eliminate bugs introduced
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* in various PDC revisions. The code is much more maintainable
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* and reliable this way vs having to debug on every version of PDC
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* on every box.
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*/
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#include <linux/capability.h>
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#include <linux/init.h>
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#include <linux/proc_fs.h>
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#include <linux/miscdevice.h>
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#include <linux/spinlock.h>
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#include <linux/uaccess.h>
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#include <asm/perf.h>
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#include <asm/parisc-device.h>
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#include <asm/processor.h>
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#include <asm/runway.h>
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#include <asm/io.h> /* for __raw_read() */
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#include "perf_images.h"
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#define MAX_RDR_WORDS 24
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#define PERF_VERSION 2 /* derived from hpux's PI v2 interface */
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/* definition of RDR regs */
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struct rdr_tbl_ent {
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uint16_t width;
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uint8_t num_words;
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uint8_t write_control;
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};
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static int perf_processor_interface __read_mostly = UNKNOWN_INTF;
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static int perf_enabled __read_mostly;
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static DEFINE_SPINLOCK(perf_lock);
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struct parisc_device *cpu_device __read_mostly;
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/* RDRs to write for PCX-W */
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static const int perf_rdrs_W[] =
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{ 0, 1, 4, 5, 6, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, -1 };
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/* RDRs to write for PCX-U */
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static const int perf_rdrs_U[] =
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{ 0, 1, 4, 5, 6, 7, 16, 17, 18, 20, 21, 22, 23, 24, 25, -1 };
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/* RDR register descriptions for PCX-W */
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static const struct rdr_tbl_ent perf_rdr_tbl_W[] = {
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{ 19, 1, 8 }, /* RDR 0 */
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{ 16, 1, 16 }, /* RDR 1 */
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{ 72, 2, 0 }, /* RDR 2 */
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{ 81, 2, 0 }, /* RDR 3 */
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{ 328, 6, 0 }, /* RDR 4 */
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{ 160, 3, 0 }, /* RDR 5 */
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{ 336, 6, 0 }, /* RDR 6 */
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{ 164, 3, 0 }, /* RDR 7 */
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{ 0, 0, 0 }, /* RDR 8 */
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{ 35, 1, 0 }, /* RDR 9 */
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{ 6, 1, 0 }, /* RDR 10 */
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{ 18, 1, 0 }, /* RDR 11 */
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{ 13, 1, 0 }, /* RDR 12 */
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{ 8, 1, 0 }, /* RDR 13 */
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{ 8, 1, 0 }, /* RDR 14 */
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{ 8, 1, 0 }, /* RDR 15 */
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{ 1530, 24, 0 }, /* RDR 16 */
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{ 16, 1, 0 }, /* RDR 17 */
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{ 4, 1, 0 }, /* RDR 18 */
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{ 0, 0, 0 }, /* RDR 19 */
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{ 152, 3, 24 }, /* RDR 20 */
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{ 152, 3, 24 }, /* RDR 21 */
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{ 233, 4, 48 }, /* RDR 22 */
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{ 233, 4, 48 }, /* RDR 23 */
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{ 71, 2, 0 }, /* RDR 24 */
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{ 71, 2, 0 }, /* RDR 25 */
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{ 11, 1, 0 }, /* RDR 26 */
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{ 18, 1, 0 }, /* RDR 27 */
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{ 128, 2, 0 }, /* RDR 28 */
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{ 0, 0, 0 }, /* RDR 29 */
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{ 16, 1, 0 }, /* RDR 30 */
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{ 16, 1, 0 }, /* RDR 31 */
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};
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/* RDR register descriptions for PCX-U */
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static const struct rdr_tbl_ent perf_rdr_tbl_U[] = {
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{ 19, 1, 8 }, /* RDR 0 */
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{ 32, 1, 16 }, /* RDR 1 */
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{ 20, 1, 0 }, /* RDR 2 */
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{ 0, 0, 0 }, /* RDR 3 */
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{ 344, 6, 0 }, /* RDR 4 */
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{ 176, 3, 0 }, /* RDR 5 */
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{ 336, 6, 0 }, /* RDR 6 */
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{ 0, 0, 0 }, /* RDR 7 */
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{ 0, 0, 0 }, /* RDR 8 */
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{ 0, 0, 0 }, /* RDR 9 */
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{ 28, 1, 0 }, /* RDR 10 */
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{ 33, 1, 0 }, /* RDR 11 */
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{ 0, 0, 0 }, /* RDR 12 */
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{ 230, 4, 0 }, /* RDR 13 */
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{ 32, 1, 0 }, /* RDR 14 */
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{ 128, 2, 0 }, /* RDR 15 */
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{ 1494, 24, 0 }, /* RDR 16 */
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{ 18, 1, 0 }, /* RDR 17 */
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{ 4, 1, 0 }, /* RDR 18 */
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{ 0, 0, 0 }, /* RDR 19 */
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{ 158, 3, 24 }, /* RDR 20 */
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{ 158, 3, 24 }, /* RDR 21 */
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{ 194, 4, 48 }, /* RDR 22 */
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{ 194, 4, 48 }, /* RDR 23 */
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{ 71, 2, 0 }, /* RDR 24 */
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{ 71, 2, 0 }, /* RDR 25 */
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{ 28, 1, 0 }, /* RDR 26 */
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{ 33, 1, 0 }, /* RDR 27 */
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{ 88, 2, 0 }, /* RDR 28 */
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{ 32, 1, 0 }, /* RDR 29 */
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{ 24, 1, 0 }, /* RDR 30 */
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{ 16, 1, 0 }, /* RDR 31 */
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};
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/*
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* A non-zero write_control in the above tables is a byte offset into
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* this array.
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*/
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static const uint64_t perf_bitmasks[] = {
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0x0000000000000000ul, /* first dbl word must be zero */
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0xfdffe00000000000ul, /* RDR0 bitmask */
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0x003f000000000000ul, /* RDR1 bitmask */
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0x00fffffffffffffful, /* RDR20-RDR21 bitmask (152 bits) */
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0xfffffffffffffffful,
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0xfffffffc00000000ul,
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0xfffffffffffffffful, /* RDR22-RDR23 bitmask (233 bits) */
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0xfffffffffffffffful,
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0xfffffffffffffffcul,
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0xff00000000000000ul
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};
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/*
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* Write control bitmasks for Pa-8700 processor given
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* some things have changed slightly.
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*/
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static const uint64_t perf_bitmasks_piranha[] = {
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0x0000000000000000ul, /* first dbl word must be zero */
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0xfdffe00000000000ul, /* RDR0 bitmask */
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0x003f000000000000ul, /* RDR1 bitmask */
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0x00fffffffffffffful, /* RDR20-RDR21 bitmask (158 bits) */
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0xfffffffffffffffful,
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0xfffffffc00000000ul,
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0xfffffffffffffffful, /* RDR22-RDR23 bitmask (210 bits) */
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0xfffffffffffffffful,
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0xfffffffffffffffful,
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0xfffc000000000000ul
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};
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static const uint64_t *bitmask_array; /* array of bitmasks to use */
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/******************************************************************************
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* Function Prototypes
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*****************************************************************************/
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static int perf_config(uint32_t *image_ptr);
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static int perf_release(struct inode *inode, struct file *file);
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static int perf_open(struct inode *inode, struct file *file);
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static ssize_t perf_read(struct file *file, char __user *buf, size_t cnt, loff_t *ppos);
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static ssize_t perf_write(struct file *file, const char __user *buf,
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size_t count, loff_t *ppos);
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static long perf_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
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static void perf_start_counters(void);
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static int perf_stop_counters(uint32_t *raddr);
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static const struct rdr_tbl_ent * perf_rdr_get_entry(uint32_t rdr_num);
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static int perf_rdr_read_ubuf(uint32_t rdr_num, uint64_t *buffer);
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static int perf_rdr_clear(uint32_t rdr_num);
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static int perf_write_image(uint64_t *memaddr);
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static void perf_rdr_write(uint32_t rdr_num, uint64_t *buffer);
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/* External Assembly Routines */
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extern uint64_t perf_rdr_shift_in_W (uint32_t rdr_num, uint16_t width);
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extern uint64_t perf_rdr_shift_in_U (uint32_t rdr_num, uint16_t width);
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extern void perf_rdr_shift_out_W (uint32_t rdr_num, uint64_t buffer);
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extern void perf_rdr_shift_out_U (uint32_t rdr_num, uint64_t buffer);
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extern void perf_intrigue_enable_perf_counters (void);
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extern void perf_intrigue_disable_perf_counters (void);
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/******************************************************************************
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* Function Definitions
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*****************************************************************************/
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/*
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* configure:
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*
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* Configure the cpu with a given data image. First turn off the counters,
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* then download the image, then turn the counters back on.
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*/
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static int perf_config(uint32_t *image_ptr)
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{
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long error;
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uint32_t raddr[4];
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/* Stop the counters*/
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error = perf_stop_counters(raddr);
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if (error != 0) {
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printk("perf_config: perf_stop_counters = %ld\n", error);
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return -EINVAL;
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}
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printk("Preparing to write image\n");
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/* Write the image to the chip */
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error = perf_write_image((uint64_t *)image_ptr);
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if (error != 0) {
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printk("perf_config: DOWNLOAD = %ld\n", error);
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return -EINVAL;
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}
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printk("Preparing to start counters\n");
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/* Start the counters */
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perf_start_counters();
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return sizeof(uint32_t);
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}
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/*
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* Open the device and initialize all of its memory. The device is only
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* opened once, but can be "queried" by multiple processes that know its
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* file descriptor.
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*/
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static int perf_open(struct inode *inode, struct file *file)
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{
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spin_lock(&perf_lock);
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if (perf_enabled) {
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spin_unlock(&perf_lock);
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return -EBUSY;
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}
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perf_enabled = 1;
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spin_unlock(&perf_lock);
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return 0;
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}
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/*
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* Close the device.
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*/
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static int perf_release(struct inode *inode, struct file *file)
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{
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spin_lock(&perf_lock);
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perf_enabled = 0;
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spin_unlock(&perf_lock);
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return 0;
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}
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/*
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* Read does nothing for this driver
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*/
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static ssize_t perf_read(struct file *file, char __user *buf, size_t cnt, loff_t *ppos)
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{
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return 0;
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}
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/*
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* write:
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*
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* This routine downloads the image to the chip. It must be
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* called on the processor that the download should happen
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* on.
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*/
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static ssize_t perf_write(struct file *file, const char __user *buf,
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size_t count, loff_t *ppos)
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{
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size_t image_size;
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uint32_t image_type;
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uint32_t interface_type;
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uint32_t test;
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if (perf_processor_interface == ONYX_INTF)
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image_size = PCXU_IMAGE_SIZE;
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else if (perf_processor_interface == CUDA_INTF)
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image_size = PCXW_IMAGE_SIZE;
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else
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return -EFAULT;
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if (!perfmon_capable())
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return -EACCES;
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if (count != sizeof(uint32_t))
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return -EIO;
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if (copy_from_user(&image_type, buf, sizeof(uint32_t)))
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return -EFAULT;
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/* Get the interface type and test type */
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interface_type = (image_type >> 16) & 0xffff;
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test = (image_type & 0xffff);
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/* Make sure everything makes sense */
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/* First check the machine type is correct for
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the requested image */
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if (((perf_processor_interface == CUDA_INTF) &&
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(interface_type != CUDA_INTF)) ||
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((perf_processor_interface == ONYX_INTF) &&
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(interface_type != ONYX_INTF)))
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return -EINVAL;
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/* Next check to make sure the requested image
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is valid */
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if (((interface_type == CUDA_INTF) &&
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(test >= MAX_CUDA_IMAGES)) ||
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((interface_type == ONYX_INTF) &&
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(test >= MAX_ONYX_IMAGES)))
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return -EINVAL;
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/* Copy the image into the processor */
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if (interface_type == CUDA_INTF)
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return perf_config(cuda_images[test]);
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else
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return perf_config(onyx_images[test]);
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return count;
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}
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/*
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* Patch the images that need to know the IVA addresses.
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*/
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static void perf_patch_images(void)
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{
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#if 0 /* FIXME!! */
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/*
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* NOTE: this routine is VERY specific to the current TLB image.
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* If the image is changed, this routine might also need to be changed.
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*/
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extern void $i_itlb_miss_2_0();
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extern void $i_dtlb_miss_2_0();
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extern void PA2_0_iva();
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/*
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* We can only use the lower 32-bits, the upper 32-bits should be 0
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* anyway given this is in the kernel
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*/
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uint32_t itlb_addr = (uint32_t)&($i_itlb_miss_2_0);
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uint32_t dtlb_addr = (uint32_t)&($i_dtlb_miss_2_0);
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uint32_t IVAaddress = (uint32_t)&PA2_0_iva;
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if (perf_processor_interface == ONYX_INTF) {
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/* clear last 2 bytes */
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onyx_images[TLBMISS][15] &= 0xffffff00;
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/* set 2 bytes */
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onyx_images[TLBMISS][15] |= (0x000000ff&((dtlb_addr) >> 24));
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onyx_images[TLBMISS][16] = (dtlb_addr << 8)&0xffffff00;
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onyx_images[TLBMISS][17] = itlb_addr;
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/* clear last 2 bytes */
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onyx_images[TLBHANDMISS][15] &= 0xffffff00;
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/* set 2 bytes */
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onyx_images[TLBHANDMISS][15] |= (0x000000ff&((dtlb_addr) >> 24));
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onyx_images[TLBHANDMISS][16] = (dtlb_addr << 8)&0xffffff00;
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onyx_images[TLBHANDMISS][17] = itlb_addr;
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/* clear last 2 bytes */
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onyx_images[BIG_CPI][15] &= 0xffffff00;
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/* set 2 bytes */
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onyx_images[BIG_CPI][15] |= (0x000000ff&((dtlb_addr) >> 24));
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onyx_images[BIG_CPI][16] = (dtlb_addr << 8)&0xffffff00;
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onyx_images[BIG_CPI][17] = itlb_addr;
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onyx_images[PANIC][15] &= 0xffffff00; /* clear last 2 bytes */
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onyx_images[PANIC][15] |= (0x000000ff&((IVAaddress) >> 24)); /* set 2 bytes */
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onyx_images[PANIC][16] = (IVAaddress << 8)&0xffffff00;
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} else if (perf_processor_interface == CUDA_INTF) {
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/* Cuda interface */
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cuda_images[TLBMISS][16] =
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(cuda_images[TLBMISS][16]&0xffff0000) |
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((dtlb_addr >> 8)&0x0000ffff);
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cuda_images[TLBMISS][17] =
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((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff);
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cuda_images[TLBMISS][18] = (itlb_addr << 16)&0xffff0000;
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cuda_images[TLBHANDMISS][16] =
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(cuda_images[TLBHANDMISS][16]&0xffff0000) |
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((dtlb_addr >> 8)&0x0000ffff);
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cuda_images[TLBHANDMISS][17] =
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((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff);
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cuda_images[TLBHANDMISS][18] = (itlb_addr << 16)&0xffff0000;
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cuda_images[BIG_CPI][16] =
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(cuda_images[BIG_CPI][16]&0xffff0000) |
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((dtlb_addr >> 8)&0x0000ffff);
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cuda_images[BIG_CPI][17] =
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((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff);
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cuda_images[BIG_CPI][18] = (itlb_addr << 16)&0xffff0000;
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} else {
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/* Unknown type */
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}
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#endif
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}
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/*
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* ioctl routine
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* All routines effect the processor that they are executed on. Thus you
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* must be running on the processor that you wish to change.
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*/
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static long perf_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
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{
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long error_start;
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uint32_t raddr[4];
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int error = 0;
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switch (cmd) {
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case PA_PERF_ON:
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/* Start the counters */
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perf_start_counters();
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break;
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case PA_PERF_OFF:
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error_start = perf_stop_counters(raddr);
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if (error_start != 0) {
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printk(KERN_ERR "perf_off: perf_stop_counters = %ld\n", error_start);
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error = -EFAULT;
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break;
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}
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/* copy out the Counters */
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if (copy_to_user((void __user *)arg, raddr,
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sizeof (raddr)) != 0) {
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error = -EFAULT;
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break;
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}
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break;
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case PA_PERF_VERSION:
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/* Return the version # */
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error = put_user(PERF_VERSION, (int *)arg);
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break;
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default:
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error = -ENOTTY;
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}
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return error;
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}
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static const struct file_operations perf_fops = {
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.llseek = no_llseek,
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.read = perf_read,
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.write = perf_write,
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.unlocked_ioctl = perf_ioctl,
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.compat_ioctl = perf_ioctl,
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.open = perf_open,
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.release = perf_release
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};
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static struct miscdevice perf_dev = {
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MISC_DYNAMIC_MINOR,
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PA_PERF_DEV,
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&perf_fops
|
|
};
|
|
|
|
/*
|
|
* Initialize the module
|
|
*/
|
|
static int __init perf_init(void)
|
|
{
|
|
int ret;
|
|
|
|
/* Determine correct processor interface to use */
|
|
bitmask_array = perf_bitmasks;
|
|
|
|
if (boot_cpu_data.cpu_type == pcxu ||
|
|
boot_cpu_data.cpu_type == pcxu_) {
|
|
perf_processor_interface = ONYX_INTF;
|
|
} else if (boot_cpu_data.cpu_type == pcxw ||
|
|
boot_cpu_data.cpu_type == pcxw_ ||
|
|
boot_cpu_data.cpu_type == pcxw2 ||
|
|
boot_cpu_data.cpu_type == mako ||
|
|
boot_cpu_data.cpu_type == mako2) {
|
|
perf_processor_interface = CUDA_INTF;
|
|
if (boot_cpu_data.cpu_type == pcxw2 ||
|
|
boot_cpu_data.cpu_type == mako ||
|
|
boot_cpu_data.cpu_type == mako2)
|
|
bitmask_array = perf_bitmasks_piranha;
|
|
} else {
|
|
perf_processor_interface = UNKNOWN_INTF;
|
|
printk("Performance monitoring counters not supported on this processor\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
ret = misc_register(&perf_dev);
|
|
if (ret) {
|
|
printk(KERN_ERR "Performance monitoring counters: "
|
|
"cannot register misc device.\n");
|
|
return ret;
|
|
}
|
|
|
|
/* Patch the images to match the system */
|
|
perf_patch_images();
|
|
|
|
/* TODO: this only lets us access the first cpu.. what to do for SMP? */
|
|
cpu_device = per_cpu(cpu_data, 0).dev;
|
|
printk("Performance monitoring counters enabled for %s\n",
|
|
per_cpu(cpu_data, 0).dev->name);
|
|
|
|
return 0;
|
|
}
|
|
device_initcall(perf_init);
|
|
|
|
/*
|
|
* perf_start_counters(void)
|
|
*
|
|
* Start the counters.
|
|
*/
|
|
static void perf_start_counters(void)
|
|
{
|
|
/* Enable performance monitor counters */
|
|
perf_intrigue_enable_perf_counters();
|
|
}
|
|
|
|
/*
|
|
* perf_stop_counters
|
|
*
|
|
* Stop the performance counters and save counts
|
|
* in a per_processor array.
|
|
*/
|
|
static int perf_stop_counters(uint32_t *raddr)
|
|
{
|
|
uint64_t userbuf[MAX_RDR_WORDS];
|
|
|
|
/* Disable performance counters */
|
|
perf_intrigue_disable_perf_counters();
|
|
|
|
if (perf_processor_interface == ONYX_INTF) {
|
|
uint64_t tmp64;
|
|
/*
|
|
* Read the counters
|
|
*/
|
|
if (!perf_rdr_read_ubuf(16, userbuf))
|
|
return -13;
|
|
|
|
/* Counter0 is bits 1398 to 1429 */
|
|
tmp64 = (userbuf[21] << 22) & 0x00000000ffc00000;
|
|
tmp64 |= (userbuf[22] >> 42) & 0x00000000003fffff;
|
|
/* OR sticky0 (bit 1430) to counter0 bit 32 */
|
|
tmp64 |= (userbuf[22] >> 10) & 0x0000000080000000;
|
|
raddr[0] = (uint32_t)tmp64;
|
|
|
|
/* Counter1 is bits 1431 to 1462 */
|
|
tmp64 = (userbuf[22] >> 9) & 0x00000000ffffffff;
|
|
/* OR sticky1 (bit 1463) to counter1 bit 32 */
|
|
tmp64 |= (userbuf[22] << 23) & 0x0000000080000000;
|
|
raddr[1] = (uint32_t)tmp64;
|
|
|
|
/* Counter2 is bits 1464 to 1495 */
|
|
tmp64 = (userbuf[22] << 24) & 0x00000000ff000000;
|
|
tmp64 |= (userbuf[23] >> 40) & 0x0000000000ffffff;
|
|
/* OR sticky2 (bit 1496) to counter2 bit 32 */
|
|
tmp64 |= (userbuf[23] >> 8) & 0x0000000080000000;
|
|
raddr[2] = (uint32_t)tmp64;
|
|
|
|
/* Counter3 is bits 1497 to 1528 */
|
|
tmp64 = (userbuf[23] >> 7) & 0x00000000ffffffff;
|
|
/* OR sticky3 (bit 1529) to counter3 bit 32 */
|
|
tmp64 |= (userbuf[23] << 25) & 0x0000000080000000;
|
|
raddr[3] = (uint32_t)tmp64;
|
|
|
|
/*
|
|
* Zero out the counters
|
|
*/
|
|
|
|
/*
|
|
* The counters and sticky-bits comprise the last 132 bits
|
|
* (1398 - 1529) of RDR16 on a U chip. We'll zero these
|
|
* out the easy way: zero out last 10 bits of dword 21,
|
|
* all of dword 22 and 58 bits (plus 6 don't care bits) of
|
|
* dword 23.
|
|
*/
|
|
userbuf[21] &= 0xfffffffffffffc00ul; /* 0 to last 10 bits */
|
|
userbuf[22] = 0;
|
|
userbuf[23] = 0;
|
|
|
|
/*
|
|
* Write back the zeroed bytes + the image given
|
|
* the read was destructive.
|
|
*/
|
|
perf_rdr_write(16, userbuf);
|
|
} else {
|
|
|
|
/*
|
|
* Read RDR-15 which contains the counters and sticky bits
|
|
*/
|
|
if (!perf_rdr_read_ubuf(15, userbuf)) {
|
|
return -13;
|
|
}
|
|
|
|
/*
|
|
* Clear out the counters
|
|
*/
|
|
perf_rdr_clear(15);
|
|
|
|
/*
|
|
* Copy the counters
|
|
*/
|
|
raddr[0] = (uint32_t)((userbuf[0] >> 32) & 0x00000000ffffffffUL);
|
|
raddr[1] = (uint32_t)(userbuf[0] & 0x00000000ffffffffUL);
|
|
raddr[2] = (uint32_t)((userbuf[1] >> 32) & 0x00000000ffffffffUL);
|
|
raddr[3] = (uint32_t)(userbuf[1] & 0x00000000ffffffffUL);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* perf_rdr_get_entry
|
|
*
|
|
* Retrieve a pointer to the description of what this
|
|
* RDR contains.
|
|
*/
|
|
static const struct rdr_tbl_ent * perf_rdr_get_entry(uint32_t rdr_num)
|
|
{
|
|
if (perf_processor_interface == ONYX_INTF) {
|
|
return &perf_rdr_tbl_U[rdr_num];
|
|
} else {
|
|
return &perf_rdr_tbl_W[rdr_num];
|
|
}
|
|
}
|
|
|
|
/*
|
|
* perf_rdr_read_ubuf
|
|
*
|
|
* Read the RDR value into the buffer specified.
|
|
*/
|
|
static int perf_rdr_read_ubuf(uint32_t rdr_num, uint64_t *buffer)
|
|
{
|
|
uint64_t data, data_mask = 0;
|
|
uint32_t width, xbits, i;
|
|
const struct rdr_tbl_ent *tentry;
|
|
|
|
tentry = perf_rdr_get_entry(rdr_num);
|
|
if ((width = tentry->width) == 0)
|
|
return 0;
|
|
|
|
/* Clear out buffer */
|
|
i = tentry->num_words;
|
|
while (i--) {
|
|
buffer[i] = 0;
|
|
}
|
|
|
|
/* Check for bits an even number of 64 */
|
|
if ((xbits = width & 0x03f) != 0) {
|
|
data_mask = 1;
|
|
data_mask <<= (64 - xbits);
|
|
data_mask--;
|
|
}
|
|
|
|
/* Grab all of the data */
|
|
i = tentry->num_words;
|
|
while (i--) {
|
|
|
|
if (perf_processor_interface == ONYX_INTF) {
|
|
data = perf_rdr_shift_in_U(rdr_num, width);
|
|
} else {
|
|
data = perf_rdr_shift_in_W(rdr_num, width);
|
|
}
|
|
if (xbits) {
|
|
buffer[i] |= (data << (64 - xbits));
|
|
if (i) {
|
|
buffer[i-1] |= ((data >> xbits) & data_mask);
|
|
}
|
|
} else {
|
|
buffer[i] = data;
|
|
}
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
|
|
/*
|
|
* perf_rdr_clear
|
|
*
|
|
* Zero out the given RDR register
|
|
*/
|
|
static int perf_rdr_clear(uint32_t rdr_num)
|
|
{
|
|
const struct rdr_tbl_ent *tentry;
|
|
int32_t i;
|
|
|
|
tentry = perf_rdr_get_entry(rdr_num);
|
|
|
|
if (tentry->width == 0) {
|
|
return -1;
|
|
}
|
|
|
|
i = tentry->num_words;
|
|
while (i--) {
|
|
if (perf_processor_interface == ONYX_INTF) {
|
|
perf_rdr_shift_out_U(rdr_num, 0UL);
|
|
} else {
|
|
perf_rdr_shift_out_W(rdr_num, 0UL);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
* perf_write_image
|
|
*
|
|
* Write the given image out to the processor
|
|
*/
|
|
static int perf_write_image(uint64_t *memaddr)
|
|
{
|
|
uint64_t buffer[MAX_RDR_WORDS];
|
|
uint64_t *bptr;
|
|
uint32_t dwords;
|
|
const uint32_t *intrigue_rdr;
|
|
const uint64_t *intrigue_bitmask;
|
|
uint64_t tmp64;
|
|
void __iomem *runway;
|
|
const struct rdr_tbl_ent *tentry;
|
|
int i;
|
|
|
|
/* Clear out counters */
|
|
if (perf_processor_interface == ONYX_INTF) {
|
|
|
|
perf_rdr_clear(16);
|
|
|
|
/* Toggle performance monitor */
|
|
perf_intrigue_enable_perf_counters();
|
|
perf_intrigue_disable_perf_counters();
|
|
|
|
intrigue_rdr = perf_rdrs_U;
|
|
} else {
|
|
perf_rdr_clear(15);
|
|
intrigue_rdr = perf_rdrs_W;
|
|
}
|
|
|
|
/* Write all RDRs */
|
|
while (*intrigue_rdr != -1) {
|
|
tentry = perf_rdr_get_entry(*intrigue_rdr);
|
|
perf_rdr_read_ubuf(*intrigue_rdr, buffer);
|
|
bptr = &buffer[0];
|
|
dwords = tentry->num_words;
|
|
if (tentry->write_control) {
|
|
intrigue_bitmask = &bitmask_array[tentry->write_control >> 3];
|
|
while (dwords--) {
|
|
tmp64 = *intrigue_bitmask & *memaddr++;
|
|
tmp64 |= (~(*intrigue_bitmask++)) & *bptr;
|
|
*bptr++ = tmp64;
|
|
}
|
|
} else {
|
|
while (dwords--) {
|
|
*bptr++ = *memaddr++;
|
|
}
|
|
}
|
|
|
|
perf_rdr_write(*intrigue_rdr, buffer);
|
|
intrigue_rdr++;
|
|
}
|
|
|
|
/*
|
|
* Now copy out the Runway stuff which is not in RDRs
|
|
*/
|
|
|
|
if (cpu_device == NULL)
|
|
{
|
|
printk(KERN_ERR "write_image: cpu_device not yet initialized!\n");
|
|
return -1;
|
|
}
|
|
|
|
runway = ioremap(cpu_device->hpa.start, 4096);
|
|
if (!runway) {
|
|
pr_err("perf_write_image: ioremap failed!\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/* Merge intrigue bits into Runway STATUS 0 */
|
|
tmp64 = __raw_readq(runway + RUNWAY_STATUS) & 0xffecfffffffffffful;
|
|
__raw_writeq(tmp64 | (*memaddr++ & 0x0013000000000000ul),
|
|
runway + RUNWAY_STATUS);
|
|
|
|
/* Write RUNWAY DEBUG registers */
|
|
for (i = 0; i < 8; i++) {
|
|
__raw_writeq(*memaddr++, runway + RUNWAY_DEBUG);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* perf_rdr_write
|
|
*
|
|
* Write the given RDR register with the contents
|
|
* of the given buffer.
|
|
*/
|
|
static void perf_rdr_write(uint32_t rdr_num, uint64_t *buffer)
|
|
{
|
|
const struct rdr_tbl_ent *tentry;
|
|
int32_t i;
|
|
|
|
printk("perf_rdr_write\n");
|
|
tentry = perf_rdr_get_entry(rdr_num);
|
|
if (tentry->width == 0) { return; }
|
|
|
|
i = tentry->num_words;
|
|
while (i--) {
|
|
if (perf_processor_interface == ONYX_INTF) {
|
|
perf_rdr_shift_out_U(rdr_num, buffer[i]);
|
|
} else {
|
|
perf_rdr_shift_out_W(rdr_num, buffer[i]);
|
|
}
|
|
}
|
|
printk("perf_rdr_write done\n");
|
|
}
|