633 lines
17 KiB
C
633 lines
17 KiB
C
/***********************license start***************
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* Author: Cavium Networks
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*
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2008 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Networks for more information
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***********************license end**************************************/
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/*
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* Support library for the hardware Packet Output unit.
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*/
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-config.h>
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#include <asm/octeon/cvmx-pko.h>
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#include <asm/octeon/cvmx-helper.h>
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/*
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* Internal state of packet output
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*/
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static int __cvmx_pko_int(int interface, int index)
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{
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switch (interface) {
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case 0:
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return index;
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case 1:
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return 4;
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case 2:
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return index + 0x08;
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case 3:
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return index + 0x0c;
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case 4:
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return index + 0x10;
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case 5:
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return 0x1c;
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case 6:
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return 0x1d;
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case 7:
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return 0x1e;
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case 8:
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return 0x1f;
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default:
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return -1;
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}
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}
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static void __cvmx_pko_iport_config(int pko_port)
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{
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int queue;
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const int num_queues = 1;
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const int base_queue = pko_port;
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const int static_priority_end = 1;
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const int static_priority_base = 1;
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for (queue = 0; queue < num_queues; queue++) {
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union cvmx_pko_mem_iqueue_ptrs config;
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cvmx_cmd_queue_result_t cmd_res;
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uint64_t *buf_ptr;
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config.u64 = 0;
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config.s.index = queue;
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config.s.qid = base_queue + queue;
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config.s.ipid = pko_port;
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config.s.tail = (queue == (num_queues - 1));
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config.s.s_tail = (queue == static_priority_end);
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config.s.static_p = (static_priority_base >= 0);
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config.s.static_q = (queue <= static_priority_end);
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config.s.qos_mask = 0xff;
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cmd_res = cvmx_cmd_queue_initialize(
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CVMX_CMD_QUEUE_PKO(base_queue + queue),
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CVMX_PKO_MAX_QUEUE_DEPTH,
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CVMX_FPA_OUTPUT_BUFFER_POOL,
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(CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE -
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CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST * 8));
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WARN(cmd_res,
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"%s: cmd_res=%d pko_port=%d base_queue=%d num_queues=%d queue=%d\n",
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__func__, (int)cmd_res, pko_port, base_queue,
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num_queues, queue);
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buf_ptr = (uint64_t *)cvmx_cmd_queue_buffer(
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CVMX_CMD_QUEUE_PKO(base_queue + queue));
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config.s.buf_ptr = cvmx_ptr_to_phys(buf_ptr) >> 7;
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CVMX_SYNCWS;
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cvmx_write_csr(CVMX_PKO_MEM_IQUEUE_PTRS, config.u64);
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}
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}
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static void __cvmx_pko_queue_alloc_o68(void)
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{
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int port;
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for (port = 0; port < 48; port++)
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__cvmx_pko_iport_config(port);
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}
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static void __cvmx_pko_port_map_o68(void)
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{
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int port;
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int interface, index;
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cvmx_helper_interface_mode_t mode;
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union cvmx_pko_mem_iport_ptrs config;
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/*
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* Initialize every iport with the invalid eid.
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*/
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config.u64 = 0;
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config.s.eid = 31; /* Invalid */
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for (port = 0; port < 128; port++) {
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config.s.ipid = port;
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cvmx_write_csr(CVMX_PKO_MEM_IPORT_PTRS, config.u64);
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}
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/*
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* Set up PKO_MEM_IPORT_PTRS
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*/
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for (port = 0; port < 48; port++) {
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interface = cvmx_helper_get_interface_num(port);
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index = cvmx_helper_get_interface_index_num(port);
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mode = cvmx_helper_interface_get_mode(interface);
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if (mode == CVMX_HELPER_INTERFACE_MODE_DISABLED)
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continue;
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config.s.ipid = port;
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config.s.qos_mask = 0xff;
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config.s.crc = 1;
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config.s.min_pkt = 1;
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config.s.intr = __cvmx_pko_int(interface, index);
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config.s.eid = config.s.intr;
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config.s.pipe = (mode == CVMX_HELPER_INTERFACE_MODE_LOOP) ?
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index : port;
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cvmx_write_csr(CVMX_PKO_MEM_IPORT_PTRS, config.u64);
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}
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}
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static void __cvmx_pko_chip_init(void)
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{
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int i;
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if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
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__cvmx_pko_port_map_o68();
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__cvmx_pko_queue_alloc_o68();
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return;
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}
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/*
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* Initialize queues
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*/
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for (i = 0; i < CVMX_PKO_MAX_OUTPUT_QUEUES; i++) {
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const uint64_t priority = 8;
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cvmx_pko_config_port(CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID, i, 1,
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&priority);
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}
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}
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/*
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* Call before any other calls to initialize the packet
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* output system. This does chip global config, and should only be
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* done by one core.
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*/
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void cvmx_pko_initialize_global(void)
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{
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union cvmx_pko_reg_cmd_buf config;
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/*
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* Set the size of the PKO command buffers to an odd number of
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* 64bit words. This allows the normal two word send to stay
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* aligned and never span a command word buffer.
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*/
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config.u64 = 0;
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config.s.pool = CVMX_FPA_OUTPUT_BUFFER_POOL;
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config.s.size = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE / 8 - 1;
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cvmx_write_csr(CVMX_PKO_REG_CMD_BUF, config.u64);
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/*
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* Chip-specific setup.
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*/
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__cvmx_pko_chip_init();
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/*
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* If we aren't using all of the queues optimize PKO's
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* internal memory.
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*/
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if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)
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|| OCTEON_IS_MODEL(OCTEON_CN56XX)
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|| OCTEON_IS_MODEL(OCTEON_CN52XX)) {
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int num_interfaces = cvmx_helper_get_number_of_interfaces();
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int last_port =
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cvmx_helper_get_last_ipd_port(num_interfaces - 1);
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int max_queues =
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cvmx_pko_get_base_queue(last_port) +
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cvmx_pko_get_num_queues(last_port);
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if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
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if (max_queues <= 32)
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cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2);
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else if (max_queues <= 64)
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cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1);
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} else {
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if (max_queues <= 64)
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cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2);
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else if (max_queues <= 128)
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cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1);
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}
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}
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}
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/*
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* Enables the packet output hardware. It must already be
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* configured.
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*/
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void cvmx_pko_enable(void)
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{
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union cvmx_pko_reg_flags flags;
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flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS);
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if (flags.s.ena_pko)
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cvmx_dprintf
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("Warning: Enabling PKO when PKO already enabled.\n");
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flags.s.ena_dwb = 1;
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flags.s.ena_pko = 1;
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/*
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* always enable big endian for 3-word command. Does nothing
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* for 2-word.
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*/
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flags.s.store_be = 1;
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cvmx_write_csr(CVMX_PKO_REG_FLAGS, flags.u64);
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}
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/*
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* Disables the packet output. Does not affect any configuration.
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*/
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void cvmx_pko_disable(void)
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{
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union cvmx_pko_reg_flags pko_reg_flags;
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pko_reg_flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS);
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pko_reg_flags.s.ena_pko = 0;
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cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64);
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}
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EXPORT_SYMBOL_GPL(cvmx_pko_disable);
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/*
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* Reset the packet output.
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*/
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static void __cvmx_pko_reset(void)
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{
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union cvmx_pko_reg_flags pko_reg_flags;
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pko_reg_flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS);
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pko_reg_flags.s.reset = 1;
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cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64);
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}
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/*
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* Shutdown and free resources required by packet output.
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*/
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void cvmx_pko_shutdown(void)
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{
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union cvmx_pko_mem_queue_ptrs config;
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int queue;
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cvmx_pko_disable();
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for (queue = 0; queue < CVMX_PKO_MAX_OUTPUT_QUEUES; queue++) {
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config.u64 = 0;
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config.s.tail = 1;
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config.s.index = 0;
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config.s.port = CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID;
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config.s.queue = queue & 0x7f;
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config.s.qos_mask = 0;
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config.s.buf_ptr = 0;
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if (!OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
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union cvmx_pko_reg_queue_ptrs1 config1;
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config1.u64 = 0;
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config1.s.qid7 = queue >> 7;
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cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64);
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}
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cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64);
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cvmx_cmd_queue_shutdown(CVMX_CMD_QUEUE_PKO(queue));
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}
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__cvmx_pko_reset();
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}
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EXPORT_SYMBOL_GPL(cvmx_pko_shutdown);
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/*
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* Configure a output port and the associated queues for use.
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*
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* @port: Port to configure.
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* @base_queue: First queue number to associate with this port.
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* @num_queues: Number of queues to associate with this port
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* @priority: Array of priority levels for each queue. Values are
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* allowed to be 0-8. A value of 8 get 8 times the traffic
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* of a value of 1. A value of 0 indicates that no rounds
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* will be participated in. These priorities can be changed
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* on the fly while the pko is enabled. A priority of 9
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* indicates that static priority should be used. If static
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* priority is used all queues with static priority must be
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* contiguous starting at the base_queue, and lower numbered
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* queues have higher priority than higher numbered queues.
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* There must be num_queues elements in the array.
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*/
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cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue,
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uint64_t num_queues,
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const uint64_t priority[])
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{
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cvmx_pko_status_t result_code;
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uint64_t queue;
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union cvmx_pko_mem_queue_ptrs config;
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union cvmx_pko_reg_queue_ptrs1 config1;
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int static_priority_base = -1;
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int static_priority_end = -1;
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if (OCTEON_IS_MODEL(OCTEON_CN68XX))
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return CVMX_PKO_SUCCESS;
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if ((port >= CVMX_PKO_NUM_OUTPUT_PORTS)
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&& (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID)) {
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cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid port %llu\n",
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(unsigned long long)port);
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return CVMX_PKO_INVALID_PORT;
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}
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if (base_queue + num_queues > CVMX_PKO_MAX_OUTPUT_QUEUES) {
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cvmx_dprintf
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("ERROR: cvmx_pko_config_port: Invalid queue range %llu\n",
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(unsigned long long)(base_queue + num_queues));
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return CVMX_PKO_INVALID_QUEUE;
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}
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if (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID) {
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/*
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* Validate the static queue priority setup and set
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* static_priority_base and static_priority_end
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* accordingly.
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*/
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for (queue = 0; queue < num_queues; queue++) {
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/* Find first queue of static priority */
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if (static_priority_base == -1
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&& priority[queue] ==
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CVMX_PKO_QUEUE_STATIC_PRIORITY)
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static_priority_base = queue;
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/* Find last queue of static priority */
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if (static_priority_base != -1
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&& static_priority_end == -1
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&& priority[queue] != CVMX_PKO_QUEUE_STATIC_PRIORITY
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&& queue)
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static_priority_end = queue - 1;
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else if (static_priority_base != -1
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&& static_priority_end == -1
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&& queue == num_queues - 1)
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/* all queues are static priority */
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static_priority_end = queue;
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/*
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* Check to make sure all static priority
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* queues are contiguous. Also catches some
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* cases of static priorites not starting at
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* queue 0.
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*/
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if (static_priority_end != -1
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&& (int)queue > static_priority_end
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&& priority[queue] ==
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CVMX_PKO_QUEUE_STATIC_PRIORITY) {
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cvmx_dprintf("ERROR: cvmx_pko_config_port: "
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"Static priority queues aren't "
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"contiguous or don't start at "
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"base queue. q: %d, eq: %d\n",
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(int)queue, static_priority_end);
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return CVMX_PKO_INVALID_PRIORITY;
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}
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}
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if (static_priority_base > 0) {
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cvmx_dprintf("ERROR: cvmx_pko_config_port: Static "
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"priority queues don't start at base "
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"queue. sq: %d\n",
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static_priority_base);
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return CVMX_PKO_INVALID_PRIORITY;
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}
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#if 0
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cvmx_dprintf("Port %d: Static priority queue base: %d, "
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"end: %d\n", port,
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static_priority_base, static_priority_end);
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#endif
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}
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/*
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* At this point, static_priority_base and static_priority_end
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* are either both -1, or are valid start/end queue
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* numbers.
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*/
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result_code = CVMX_PKO_SUCCESS;
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#ifdef PKO_DEBUG
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cvmx_dprintf("num queues: %d (%lld,%lld)\n", num_queues,
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CVMX_PKO_QUEUES_PER_PORT_INTERFACE0,
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CVMX_PKO_QUEUES_PER_PORT_INTERFACE1);
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#endif
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for (queue = 0; queue < num_queues; queue++) {
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uint64_t *buf_ptr = NULL;
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config1.u64 = 0;
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config1.s.idx3 = queue >> 3;
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config1.s.qid7 = (base_queue + queue) >> 7;
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config.u64 = 0;
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config.s.tail = queue == (num_queues - 1);
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config.s.index = queue;
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config.s.port = port;
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config.s.queue = base_queue + queue;
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if (!cvmx_octeon_is_pass1()) {
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config.s.static_p = static_priority_base >= 0;
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config.s.static_q = (int)queue <= static_priority_end;
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config.s.s_tail = (int)queue == static_priority_end;
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}
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/*
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* Convert the priority into an enable bit field. Try
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* to space the bits out evenly so the packet don't
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* get grouped up
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*/
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switch ((int)priority[queue]) {
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case 0:
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config.s.qos_mask = 0x00;
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break;
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case 1:
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config.s.qos_mask = 0x01;
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break;
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case 2:
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config.s.qos_mask = 0x11;
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break;
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case 3:
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config.s.qos_mask = 0x49;
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break;
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case 4:
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config.s.qos_mask = 0x55;
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break;
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case 5:
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config.s.qos_mask = 0x57;
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break;
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case 6:
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config.s.qos_mask = 0x77;
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break;
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case 7:
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config.s.qos_mask = 0x7f;
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break;
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case 8:
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config.s.qos_mask = 0xff;
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break;
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case CVMX_PKO_QUEUE_STATIC_PRIORITY:
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if (!cvmx_octeon_is_pass1()) {
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config.s.qos_mask = 0xff;
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break;
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}
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fallthrough; /* to the error case, when Pass 1 */
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default:
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cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid "
|
|
"priority %llu\n",
|
|
(unsigned long long)priority[queue]);
|
|
config.s.qos_mask = 0xff;
|
|
result_code = CVMX_PKO_INVALID_PRIORITY;
|
|
break;
|
|
}
|
|
|
|
if (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID) {
|
|
cvmx_cmd_queue_result_t cmd_res =
|
|
cvmx_cmd_queue_initialize(CVMX_CMD_QUEUE_PKO
|
|
(base_queue + queue),
|
|
CVMX_PKO_MAX_QUEUE_DEPTH,
|
|
CVMX_FPA_OUTPUT_BUFFER_POOL,
|
|
CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE
|
|
-
|
|
CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST
|
|
* 8);
|
|
if (cmd_res != CVMX_CMD_QUEUE_SUCCESS) {
|
|
switch (cmd_res) {
|
|
case CVMX_CMD_QUEUE_NO_MEMORY:
|
|
cvmx_dprintf("ERROR: "
|
|
"cvmx_pko_config_port: "
|
|
"Unable to allocate "
|
|
"output buffer.\n");
|
|
return CVMX_PKO_NO_MEMORY;
|
|
case CVMX_CMD_QUEUE_ALREADY_SETUP:
|
|
cvmx_dprintf
|
|
("ERROR: cvmx_pko_config_port: Port already setup.\n");
|
|
return CVMX_PKO_PORT_ALREADY_SETUP;
|
|
case CVMX_CMD_QUEUE_INVALID_PARAM:
|
|
default:
|
|
cvmx_dprintf
|
|
("ERROR: cvmx_pko_config_port: Command queue initialization failed.\n");
|
|
return CVMX_PKO_CMD_QUEUE_INIT_ERROR;
|
|
}
|
|
}
|
|
|
|
buf_ptr =
|
|
(uint64_t *)
|
|
cvmx_cmd_queue_buffer(CVMX_CMD_QUEUE_PKO
|
|
(base_queue + queue));
|
|
config.s.buf_ptr = cvmx_ptr_to_phys(buf_ptr);
|
|
} else
|
|
config.s.buf_ptr = 0;
|
|
|
|
CVMX_SYNCWS;
|
|
|
|
if (!OCTEON_IS_MODEL(OCTEON_CN3XXX))
|
|
cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64);
|
|
cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64);
|
|
}
|
|
|
|
return result_code;
|
|
}
|
|
|
|
#ifdef PKO_DEBUG
|
|
/*
|
|
* Show map of ports -> queues for different cores.
|
|
*/
|
|
void cvmx_pko_show_queue_map()
|
|
{
|
|
int core, port;
|
|
int pko_output_ports = 36;
|
|
|
|
cvmx_dprintf("port");
|
|
for (port = 0; port < pko_output_ports; port++)
|
|
cvmx_dprintf("%3d ", port);
|
|
cvmx_dprintf("\n");
|
|
|
|
for (core = 0; core < CVMX_MAX_CORES; core++) {
|
|
cvmx_dprintf("\n%2d: ", core);
|
|
for (port = 0; port < pko_output_ports; port++) {
|
|
cvmx_dprintf("%3d ",
|
|
cvmx_pko_get_base_queue_per_core(port,
|
|
core));
|
|
}
|
|
}
|
|
cvmx_dprintf("\n");
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Rate limit a PKO port to a max packets/sec. This function is only
|
|
* supported on CN51XX and higher, excluding CN58XX.
|
|
*
|
|
* @port: Port to rate limit
|
|
* @packets_s: Maximum packet/sec
|
|
* @burst: Maximum number of packets to burst in a row before rate
|
|
* limiting cuts in.
|
|
*
|
|
* Returns Zero on success, negative on failure
|
|
*/
|
|
int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst)
|
|
{
|
|
union cvmx_pko_mem_port_rate0 pko_mem_port_rate0;
|
|
union cvmx_pko_mem_port_rate1 pko_mem_port_rate1;
|
|
|
|
pko_mem_port_rate0.u64 = 0;
|
|
pko_mem_port_rate0.s.pid = port;
|
|
pko_mem_port_rate0.s.rate_pkt =
|
|
cvmx_sysinfo_get()->cpu_clock_hz / packets_s / 16;
|
|
/* No cost per word since we are limited by packets/sec, not bits/sec */
|
|
pko_mem_port_rate0.s.rate_word = 0;
|
|
|
|
pko_mem_port_rate1.u64 = 0;
|
|
pko_mem_port_rate1.s.pid = port;
|
|
pko_mem_port_rate1.s.rate_lim =
|
|
((uint64_t) pko_mem_port_rate0.s.rate_pkt * burst) >> 8;
|
|
|
|
cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64);
|
|
cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Rate limit a PKO port to a max bits/sec. This function is only
|
|
* supported on CN51XX and higher, excluding CN58XX.
|
|
*
|
|
* @port: Port to rate limit
|
|
* @bits_s: PKO rate limit in bits/sec
|
|
* @burst: Maximum number of bits to burst before rate
|
|
* limiting cuts in.
|
|
*
|
|
* Returns Zero on success, negative on failure
|
|
*/
|
|
int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst)
|
|
{
|
|
union cvmx_pko_mem_port_rate0 pko_mem_port_rate0;
|
|
union cvmx_pko_mem_port_rate1 pko_mem_port_rate1;
|
|
uint64_t clock_rate = cvmx_sysinfo_get()->cpu_clock_hz;
|
|
uint64_t tokens_per_bit = clock_rate * 16 / bits_s;
|
|
|
|
pko_mem_port_rate0.u64 = 0;
|
|
pko_mem_port_rate0.s.pid = port;
|
|
/*
|
|
* Each packet has a 12 bytes of interframe gap, an 8 byte
|
|
* preamble, and a 4 byte CRC. These are not included in the
|
|
* per word count. Multiply by 8 to covert to bits and divide
|
|
* by 256 for limit granularity.
|
|
*/
|
|
pko_mem_port_rate0.s.rate_pkt = (12 + 8 + 4) * 8 * tokens_per_bit / 256;
|
|
/* Each 8 byte word has 64bits */
|
|
pko_mem_port_rate0.s.rate_word = 64 * tokens_per_bit;
|
|
|
|
pko_mem_port_rate1.u64 = 0;
|
|
pko_mem_port_rate1.s.pid = port;
|
|
pko_mem_port_rate1.s.rate_lim = tokens_per_bit * burst / 256;
|
|
|
|
cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64);
|
|
cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64);
|
|
return 0;
|
|
}
|