103 lines
4.9 KiB
C
103 lines
4.9 KiB
C
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
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/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
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*
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* Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
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*/
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#ifndef _ACP_IP_OFFSET_HEADER
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#define _ACP_IP_OFFSET_HEADER
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#define ACPAXI2AXI_ATU_CTRL 0xC40
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#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0xC20
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#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0xC24
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#define ACP_PGFSM_CONTROL 0x141C
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#define ACP_PGFSM_STATUS 0x1420
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#define ACP_SOFT_RESET 0x1000
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#define ACP_CONTROL 0x1004
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#define ACP_EXTERNAL_INTR_ENB 0x1800
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#define ACP_EXTERNAL_INTR_CNTL 0x1804
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#define ACP_EXTERNAL_INTR_STAT 0x1808
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#define ACP_I2S_PIN_CONFIG 0x1400
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#define ACP_SCRATCH_REG_0 0x12800
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/* Registers from ACP_AUDIO_BUFFERS block */
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#define ACP_I2S_RX_RINGBUFADDR 0x2000
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#define ACP_I2S_RX_RINGBUFSIZE 0x2004
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#define ACP_I2S_RX_LINKPOSITIONCNTR 0x2008
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#define ACP_I2S_RX_FIFOADDR 0x200C
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#define ACP_I2S_RX_FIFOSIZE 0x2010
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#define ACP_I2S_RX_DMA_SIZE 0x2014
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#define ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x2018
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#define ACP_I2S_RX_LINEARPOSITIONCNTR_LOW 0x201C
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#define ACP_I2S_RX_INTR_WATERMARK_SIZE 0x2020
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#define ACP_I2S_TX_RINGBUFADDR 0x2024
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#define ACP_I2S_TX_RINGBUFSIZE 0x2028
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#define ACP_I2S_TX_LINKPOSITIONCNTR 0x202C
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#define ACP_I2S_TX_FIFOADDR 0x2030
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#define ACP_I2S_TX_FIFOSIZE 0x2034
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#define ACP_I2S_TX_DMA_SIZE 0x2038
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#define ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x203C
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#define ACP_I2S_TX_LINEARPOSITIONCNTR_LOW 0x2040
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#define ACP_I2S_TX_INTR_WATERMARK_SIZE 0x2044
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#define ACP_BT_RX_RINGBUFADDR 0x2048
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#define ACP_BT_RX_RINGBUFSIZE 0x204C
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#define ACP_BT_RX_LINKPOSITIONCNTR 0x2050
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#define ACP_BT_RX_FIFOADDR 0x2054
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#define ACP_BT_RX_FIFOSIZE 0x2058
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#define ACP_BT_RX_DMA_SIZE 0x205C
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#define ACP_BT_RX_LINEARPOSITIONCNTR_HIGH 0x2060
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#define ACP_BT_RX_LINEARPOSITIONCNTR_LOW 0x2064
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#define ACP_BT_RX_INTR_WATERMARK_SIZE 0x2068
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#define ACP_BT_TX_RINGBUFADDR 0x206C
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#define ACP_BT_TX_RINGBUFSIZE 0x2070
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#define ACP_BT_TX_LINKPOSITIONCNTR 0x2074
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#define ACP_BT_TX_FIFOADDR 0x2078
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#define ACP_BT_TX_FIFOSIZE 0x207C
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#define ACP_BT_TX_DMA_SIZE 0x2080
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#define ACP_BT_TX_LINEARPOSITIONCNTR_HIGH 0x2084
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#define ACP_BT_TX_LINEARPOSITIONCNTR_LOW 0x2088
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#define ACP_BT_TX_INTR_WATERMARK_SIZE 0x208C
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#define ACP_I2STDM_IER 0x2400
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#define ACP_I2STDM_IRER 0x2404
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#define ACP_I2STDM_RXFRMT 0x2408
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#define ACP_I2STDM_ITER 0x240C
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#define ACP_I2STDM_TXFRMT 0x2410
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/* Registers from ACP_BT_TDM block */
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#define ACP_BTTDM_IER 0x2800
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#define ACP_BTTDM_IRER 0x2804
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#define ACP_BTTDM_RXFRMT 0x2808
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#define ACP_BTTDM_ITER 0x280C
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#define ACP_BTTDM_TXFRMT 0x2810
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/* Registers from ACP_WOV_PDM block */
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#define ACP_WOV_PDM_ENABLE 0x2C04
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#define ACP_WOV_PDM_DMA_ENABLE 0x2C08
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#define ACP_WOV_RX_RINGBUFADDR 0x2C0C
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#define ACP_WOV_RX_RINGBUFSIZE 0x2C10
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#define ACP_WOV_RX_LINKPOSITIONCNTR 0x2C14
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#define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH 0x2C18
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#define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW 0x2C1C
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#define ACP_WOV_RX_INTR_WATERMARK_SIZE 0x2C20
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#define ACP_WOV_PDM_FIFO_FLUSH 0x2C24
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#define ACP_WOV_PDM_NO_OF_CHANNELS 0x2C28
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#define ACP_WOV_PDM_DECIMATION_FACTOR 0x2C2C
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#define ACP_WOV_PDM_VAD_CTRL 0x2C30
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#define ACP_WOV_BUFFER_STATUS 0x2C58
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#define ACP_WOV_MISC_CTRL 0x2C5C
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#define ACP_WOV_CLK_CTRL 0x2C60
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#define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN 0x2C64
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#define ACP_WOV_ERROR_STATUS_REGISTER 0x2C68
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#endif
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