233 lines
7.6 KiB
C
233 lines
7.6 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __HAL2_H
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#define __HAL2_H
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/*
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* Driver for HAL2 sound processors
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* Copyright (c) 1999 Ulf Carlsson <ulfc@bun.falkenberg.se>
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* Copyright (c) 2001, 2002, 2003 Ladislav Michl <ladis@linux-mips.org>
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*/
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#include <linux/types.h>
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/* Indirect status register */
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#define H2_ISR_TSTATUS 0x01 /* RO: transaction status 1=busy */
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#define H2_ISR_USTATUS 0x02 /* RO: utime status bit 1=armed */
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#define H2_ISR_QUAD_MODE 0x04 /* codec mode 0=indigo 1=quad */
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#define H2_ISR_GLOBAL_RESET_N 0x08 /* chip global reset 0=reset */
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#define H2_ISR_CODEC_RESET_N 0x10 /* codec/synth reset 0=reset */
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/* Revision register */
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#define H2_REV_AUDIO_PRESENT 0x8000 /* RO: audio present 0=present */
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#define H2_REV_BOARD_M 0x7000 /* RO: bits 14:12, board revision */
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#define H2_REV_MAJOR_CHIP_M 0x00F0 /* RO: bits 7:4, major chip revision */
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#define H2_REV_MINOR_CHIP_M 0x000F /* RO: bits 3:0, minor chip revision */
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/* Indirect address register */
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/*
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* Address of indirect internal register to be accessed. A write to this
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* register initiates read or write access to the indirect registers in the
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* HAL2. Note that there af four indirect data registers for write access to
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* registers larger than 16 byte.
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*/
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#define H2_IAR_TYPE_M 0xF000 /* bits 15:12, type of functional */
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/* block the register resides in */
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/* 1=DMA Port */
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/* 9=Global DMA Control */
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/* 2=Bresenham */
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/* 3=Unix Timer */
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#define H2_IAR_NUM_M 0x0F00 /* bits 11:8 instance of the */
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/* blockin which the indirect */
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/* register resides */
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/* If IAR_TYPE_M=DMA Port: */
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/* 1=Synth In */
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/* 2=AES In */
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/* 3=AES Out */
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/* 4=DAC Out */
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/* 5=ADC Out */
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/* 6=Synth Control */
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/* If IAR_TYPE_M=Global DMA Control: */
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/* 1=Control */
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/* If IAR_TYPE_M=Bresenham: */
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/* 1=Bresenham Clock Gen 1 */
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/* 2=Bresenham Clock Gen 2 */
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/* 3=Bresenham Clock Gen 3 */
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/* If IAR_TYPE_M=Unix Timer: */
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/* 1=Unix Timer */
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#define H2_IAR_ACCESS_SELECT 0x0080 /* 1=read 0=write */
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#define H2_IAR_PARAM 0x000C /* Parameter Select */
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#define H2_IAR_RB_INDEX_M 0x0003 /* Read Back Index */
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/* 00:word0 */
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/* 01:word1 */
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/* 10:word2 */
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/* 11:word3 */
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/*
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* HAL2 internal addressing
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*
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* The HAL2 has "indirect registers" (idr) which are accessed by writing to the
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* Indirect Data registers. Write the address to the Indirect Address register
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* to transfer the data.
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*
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* We define the H2IR_* to the read address and H2IW_* to the write address and
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* H2I_* to be fields in whatever register is referred to.
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*
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* When we write to indirect registers which are larger than one word (16 bit)
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* we have to fill more than one indirect register before writing. When we read
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* back however we have to read several times, each time with different Read
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* Back Indexes (there are defs for doing this easily).
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*/
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/*
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* Relay Control
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*/
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#define H2I_RELAY_C 0x9100
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#define H2I_RELAY_C_STATE 0x01 /* state of RELAY pin signal */
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/* DMA port enable */
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#define H2I_DMA_PORT_EN 0x9104
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#define H2I_DMA_PORT_EN_SY_IN 0x01 /* Synth_in DMA port */
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#define H2I_DMA_PORT_EN_AESRX 0x02 /* AES receiver DMA port */
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#define H2I_DMA_PORT_EN_AESTX 0x04 /* AES transmitter DMA port */
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#define H2I_DMA_PORT_EN_CODECTX 0x08 /* CODEC transmit DMA port */
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#define H2I_DMA_PORT_EN_CODECR 0x10 /* CODEC receive DMA port */
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#define H2I_DMA_END 0x9108 /* global dma endian select */
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#define H2I_DMA_END_SY_IN 0x01 /* Synth_in DMA port */
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#define H2I_DMA_END_AESRX 0x02 /* AES receiver DMA port */
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#define H2I_DMA_END_AESTX 0x04 /* AES transmitter DMA port */
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#define H2I_DMA_END_CODECTX 0x08 /* CODEC transmit DMA port */
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#define H2I_DMA_END_CODECR 0x10 /* CODEC receive DMA port */
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/* 0=b_end 1=l_end */
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#define H2I_DMA_DRV 0x910C /* global PBUS DMA enable */
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#define H2I_SYNTH_C 0x1104 /* Synth DMA control */
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#define H2I_AESRX_C 0x1204 /* AES RX dma control */
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#define H2I_C_TS_EN 0x20 /* Timestamp enable */
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#define H2I_C_TS_FRMT 0x40 /* Timestamp format */
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#define H2I_C_NAUDIO 0x80 /* Sign extend */
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/* AESRX CTL, 16 bit */
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#define H2I_AESTX_C 0x1304 /* AES TX DMA control */
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#define H2I_AESTX_C_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */
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#define H2I_AESTX_C_CLKID_M 0x18
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#define H2I_AESTX_C_DATAT_SHIFT 8 /* 1=mono 2=stereo (3=quad) */
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#define H2I_AESTX_C_DATAT_M 0x300
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/* CODEC registers */
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#define H2I_DAC_C1 0x1404 /* DAC DMA control, 16 bit */
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#define H2I_DAC_C2 0x1408 /* DAC DMA control, 32 bit */
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#define H2I_ADC_C1 0x1504 /* ADC DMA control, 16 bit */
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#define H2I_ADC_C2 0x1508 /* ADC DMA control, 32 bit */
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/* Bits in CTL1 register */
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#define H2I_C1_DMA_SHIFT 0 /* DMA channel */
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#define H2I_C1_DMA_M 0x7
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#define H2I_C1_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */
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#define H2I_C1_CLKID_M 0x18
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#define H2I_C1_DATAT_SHIFT 8 /* 1=mono 2=stereo (3=quad) */
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#define H2I_C1_DATAT_M 0x300
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/* Bits in CTL2 register */
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#define H2I_C2_R_GAIN_SHIFT 0 /* right a/d input gain */
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#define H2I_C2_R_GAIN_M 0xf
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#define H2I_C2_L_GAIN_SHIFT 4 /* left a/d input gain */
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#define H2I_C2_L_GAIN_M 0xf0
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#define H2I_C2_R_SEL 0x100 /* right input select */
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#define H2I_C2_L_SEL 0x200 /* left input select */
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#define H2I_C2_MUTE 0x400 /* mute */
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#define H2I_C2_DO1 0x00010000 /* digital output port bit 0 */
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#define H2I_C2_DO2 0x00020000 /* digital output port bit 1 */
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#define H2I_C2_R_ATT_SHIFT 18 /* right d/a output - */
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#define H2I_C2_R_ATT_M 0x007c0000 /* attenuation */
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#define H2I_C2_L_ATT_SHIFT 23 /* left d/a output - */
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#define H2I_C2_L_ATT_M 0x0f800000 /* attenuation */
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#define H2I_SYNTH_MAP_C 0x1104 /* synth dma handshake ctrl */
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/* Clock generator CTL 1, 16 bit */
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#define H2I_BRES1_C1 0x2104
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#define H2I_BRES2_C1 0x2204
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#define H2I_BRES3_C1 0x2304
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#define H2I_BRES_C1_SHIFT 0 /* 0=48.0 1=44.1 2=aes_rx */
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#define H2I_BRES_C1_M 0x03
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/* Clock generator CTL 2, 32 bit */
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#define H2I_BRES1_C2 0x2108
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#define H2I_BRES2_C2 0x2208
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#define H2I_BRES3_C2 0x2308
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#define H2I_BRES_C2_INC_SHIFT 0 /* increment value */
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#define H2I_BRES_C2_INC_M 0xffff
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#define H2I_BRES_C2_MOD_SHIFT 16 /* modcontrol value */
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#define H2I_BRES_C2_MOD_M 0xffff0000 /* modctrl=0xffff&(modinc-1) */
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/* Unix timer, 64 bit */
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#define H2I_UTIME 0x3104
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#define H2I_UTIME_0_LD 0xffff /* microseconds, LSB's */
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#define H2I_UTIME_1_LD0 0x0f /* microseconds, MSB's */
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#define H2I_UTIME_1_LD1 0xf0 /* tenths of microseconds */
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#define H2I_UTIME_2_LD 0xffff /* seconds, LSB's */
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#define H2I_UTIME_3_LD 0xffff /* seconds, MSB's */
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struct hal2_ctl_regs {
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u32 _unused0[4];
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u32 isr; /* 0x10 Status Register */
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u32 _unused1[3];
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u32 rev; /* 0x20 Revision Register */
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u32 _unused2[3];
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u32 iar; /* 0x30 Indirect Address Register */
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u32 _unused3[3];
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u32 idr0; /* 0x40 Indirect Data Register 0 */
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u32 _unused4[3];
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u32 idr1; /* 0x50 Indirect Data Register 1 */
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u32 _unused5[3];
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u32 idr2; /* 0x60 Indirect Data Register 2 */
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u32 _unused6[3];
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u32 idr3; /* 0x70 Indirect Data Register 3 */
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};
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struct hal2_aes_regs {
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u32 rx_stat[2]; /* Status registers */
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u32 rx_cr[2]; /* Control registers */
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u32 rx_ud[4]; /* User data window */
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u32 rx_st[24]; /* Channel status data */
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u32 tx_stat[1]; /* Status register */
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u32 tx_cr[3]; /* Control registers */
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u32 tx_ud[4]; /* User data window */
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u32 tx_st[24]; /* Channel status data */
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};
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struct hal2_vol_regs {
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u32 right; /* Right volume */
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u32 left; /* Left volume */
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};
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struct hal2_syn_regs {
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u32 _unused0[2];
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u32 page; /* DOC Page register */
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u32 regsel; /* DOC Register selection */
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u32 dlow; /* DOC Data low */
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u32 dhigh; /* DOC Data high */
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u32 irq; /* IRQ Status */
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u32 dram; /* DRAM Access */
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};
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#endif /* __HAL2_H */
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