197 lines
6.0 KiB
C
197 lines
6.0 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_SH_MOBILE_LCDC_H__
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#define __ASM_SH_MOBILE_LCDC_H__
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#include <linux/fb.h>
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/* Register definitions */
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#define _LDDCKR 0x410
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#define LDDCKR_ICKSEL_BUS (0 << 16)
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#define LDDCKR_ICKSEL_MIPI (1 << 16)
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#define LDDCKR_ICKSEL_HDMI (2 << 16)
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#define LDDCKR_ICKSEL_EXT (3 << 16)
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#define LDDCKR_ICKSEL_MASK (7 << 16)
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#define LDDCKR_MOSEL (1 << 6)
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#define _LDDCKSTPR 0x414
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#define _LDINTR 0x468
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#define LDINTR_FE (1 << 10)
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#define LDINTR_VSE (1 << 9)
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#define LDINTR_VEE (1 << 8)
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#define LDINTR_FS (1 << 2)
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#define LDINTR_VSS (1 << 1)
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#define LDINTR_VES (1 << 0)
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#define LDINTR_STATUS_MASK (0xff << 0)
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#define _LDSR 0x46c
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#define LDSR_MSS (1 << 10)
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#define LDSR_MRS (1 << 8)
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#define LDSR_AS (1 << 1)
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#define _LDCNT1R 0x470
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#define LDCNT1R_DE (1 << 0)
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#define _LDCNT2R 0x474
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#define LDCNT2R_BR (1 << 8)
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#define LDCNT2R_MD (1 << 3)
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#define LDCNT2R_SE (1 << 2)
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#define LDCNT2R_ME (1 << 1)
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#define LDCNT2R_DO (1 << 0)
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#define _LDRCNTR 0x478
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#define LDRCNTR_SRS (1 << 17)
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#define LDRCNTR_SRC (1 << 16)
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#define LDRCNTR_MRS (1 << 1)
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#define LDRCNTR_MRC (1 << 0)
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#define _LDDDSR 0x47c
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#define LDDDSR_LS (1 << 2)
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#define LDDDSR_WS (1 << 1)
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#define LDDDSR_BS (1 << 0)
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#define LDMT1R_VPOL (1 << 28)
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#define LDMT1R_HPOL (1 << 27)
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#define LDMT1R_DWPOL (1 << 26)
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#define LDMT1R_DIPOL (1 << 25)
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#define LDMT1R_DAPOL (1 << 24)
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#define LDMT1R_HSCNT (1 << 17)
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#define LDMT1R_DWCNT (1 << 16)
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#define LDMT1R_IFM (1 << 12)
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#define LDMT1R_MIFTYP_RGB8 (0x0 << 0)
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#define LDMT1R_MIFTYP_RGB9 (0x4 << 0)
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#define LDMT1R_MIFTYP_RGB12A (0x5 << 0)
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#define LDMT1R_MIFTYP_RGB12B (0x6 << 0)
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#define LDMT1R_MIFTYP_RGB16 (0x7 << 0)
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#define LDMT1R_MIFTYP_RGB18 (0xa << 0)
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#define LDMT1R_MIFTYP_RGB24 (0xb << 0)
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#define LDMT1R_MIFTYP_YCBCR (0xf << 0)
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#define LDMT1R_MIFTYP_SYS8A (0x0 << 0)
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#define LDMT1R_MIFTYP_SYS8B (0x1 << 0)
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#define LDMT1R_MIFTYP_SYS8C (0x2 << 0)
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#define LDMT1R_MIFTYP_SYS8D (0x3 << 0)
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#define LDMT1R_MIFTYP_SYS9 (0x4 << 0)
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#define LDMT1R_MIFTYP_SYS12 (0x5 << 0)
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#define LDMT1R_MIFTYP_SYS16A (0x7 << 0)
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#define LDMT1R_MIFTYP_SYS16B (0x8 << 0)
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#define LDMT1R_MIFTYP_SYS16C (0x9 << 0)
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#define LDMT1R_MIFTYP_SYS18 (0xa << 0)
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#define LDMT1R_MIFTYP_SYS24 (0xb << 0)
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#define LDMT1R_MIFTYP_MASK (0xf << 0)
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#define LDDFR_CF1 (1 << 18)
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#define LDDFR_CF0 (1 << 17)
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#define LDDFR_CC (1 << 16)
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#define LDDFR_YF_420 (0 << 8)
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#define LDDFR_YF_422 (1 << 8)
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#define LDDFR_YF_444 (2 << 8)
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#define LDDFR_YF_MASK (3 << 8)
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#define LDDFR_PKF_ARGB32 (0x00 << 0)
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#define LDDFR_PKF_RGB16 (0x03 << 0)
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#define LDDFR_PKF_RGB24 (0x0b << 0)
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#define LDDFR_PKF_MASK (0x1f << 0)
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#define LDSM1R_OS (1 << 0)
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#define LDSM2R_OSTRG (1 << 0)
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#define LDPMR_LPS (3 << 0)
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#define _LDDWD0R 0x800
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#define LDDWDxR_WDACT (1 << 28)
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#define LDDWDxR_RSW (1 << 24)
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#define _LDDRDR 0x840
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#define LDDRDR_RSR (1 << 24)
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#define LDDRDR_DRD_MASK (0x3ffff << 0)
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#define _LDDWAR 0x900
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#define LDDWAR_WA (1 << 0)
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#define _LDDRAR 0x904
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#define LDDRAR_RA (1 << 0)
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enum {
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RGB8 = LDMT1R_MIFTYP_RGB8, /* 24bpp, 8:8:8 */
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RGB9 = LDMT1R_MIFTYP_RGB9, /* 18bpp, 9:9 */
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RGB12A = LDMT1R_MIFTYP_RGB12A, /* 24bpp, 12:12 */
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RGB12B = LDMT1R_MIFTYP_RGB12B, /* 12bpp */
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RGB16 = LDMT1R_MIFTYP_RGB16, /* 16bpp */
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RGB18 = LDMT1R_MIFTYP_RGB18, /* 18bpp */
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RGB24 = LDMT1R_MIFTYP_RGB24, /* 24bpp */
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YUV422 = LDMT1R_MIFTYP_YCBCR, /* 16bpp */
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SYS8A = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8A, /* 24bpp, 8:8:8 */
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SYS8B = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8B, /* 18bpp, 8:8:2 */
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SYS8C = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8C, /* 18bpp, 2:8:8 */
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SYS8D = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8D, /* 16bpp, 8:8 */
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SYS9 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS9, /* 18bpp, 9:9 */
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SYS12 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS12, /* 24bpp, 12:12 */
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SYS16A = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16A, /* 16bpp */
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SYS16B = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16B, /* 18bpp, 16:2 */
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SYS16C = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16C, /* 18bpp, 2:16 */
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SYS18 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS18, /* 18bpp */
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SYS24 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS24, /* 24bpp */
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};
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enum { LCDC_CHAN_DISABLED = 0,
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LCDC_CHAN_MAINLCD,
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LCDC_CHAN_SUBLCD };
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enum { LCDC_CLK_BUS, LCDC_CLK_PERIPHERAL, LCDC_CLK_EXTERNAL };
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#define LCDC_FLAGS_DWPOL (1 << 0) /* Rising edge dot clock data latch */
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#define LCDC_FLAGS_DIPOL (1 << 1) /* Active low display enable polarity */
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#define LCDC_FLAGS_DAPOL (1 << 2) /* Active low display data polarity */
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#define LCDC_FLAGS_HSCNT (1 << 3) /* Disable HSYNC during VBLANK */
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#define LCDC_FLAGS_DWCNT (1 << 4) /* Disable dotclock during blanking */
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struct sh_mobile_lcdc_sys_bus_cfg {
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unsigned long ldmt2r;
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unsigned long ldmt3r;
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unsigned long deferred_io_msec;
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};
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struct sh_mobile_lcdc_sys_bus_ops {
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void (*write_index)(void *handle, unsigned long data);
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void (*write_data)(void *handle, unsigned long data);
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unsigned long (*read_data)(void *handle);
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};
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struct sh_mobile_lcdc_panel_cfg {
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unsigned long width; /* Panel width in mm */
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unsigned long height; /* Panel height in mm */
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int (*setup_sys)(void *sys_ops_handle,
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struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
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void (*start_transfer)(void *sys_ops_handle,
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struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
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void (*display_on)(void);
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void (*display_off)(void);
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};
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/* backlight info */
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struct sh_mobile_lcdc_bl_info {
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const char *name;
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int max_brightness;
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int (*set_brightness)(int brightness);
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};
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struct sh_mobile_lcdc_overlay_cfg {
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int fourcc;
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unsigned int max_xres;
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unsigned int max_yres;
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};
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struct sh_mobile_lcdc_chan_cfg {
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int chan;
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int fourcc;
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int colorspace;
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int interface_type; /* selects RGBn or SYSn I/F, see above */
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int clock_divider;
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unsigned long flags; /* LCDC_FLAGS_... */
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const struct fb_videomode *lcd_modes;
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int num_modes;
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struct sh_mobile_lcdc_panel_cfg panel_cfg;
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struct sh_mobile_lcdc_bl_info bl_info;
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struct sh_mobile_lcdc_sys_bus_cfg sys_bus_cfg; /* only for SYSn I/F */
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struct platform_device *tx_dev; /* HDMI/DSI transmitter device */
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};
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struct sh_mobile_lcdc_info {
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int clock_source;
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struct sh_mobile_lcdc_chan_cfg ch[2];
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struct sh_mobile_lcdc_overlay_cfg overlays[4];
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};
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#endif /* __ASM_SH_MOBILE_LCDC_H__ */
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