181 lines
4.6 KiB
C
181 lines
4.6 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2014 Google, Inc.
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*/
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#ifndef _DT_BINDINGS_CLOCK_PISTACHIO_H
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#define _DT_BINDINGS_CLOCK_PISTACHIO_H
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/* PLLs */
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#define CLK_MIPS_PLL 0
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#define CLK_AUDIO_PLL 1
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#define CLK_RPU_V_PLL 2
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#define CLK_RPU_L_PLL 3
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#define CLK_SYS_PLL 4
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#define CLK_WIFI_PLL 5
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#define CLK_BT_PLL 6
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/* Fixed-factor clocks */
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#define CLK_WIFI_DIV4 16
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#define CLK_WIFI_DIV8 17
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/* Gate clocks */
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#define CLK_MIPS 32
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#define CLK_AUDIO_IN 33
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#define CLK_AUDIO 34
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#define CLK_I2S 35
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#define CLK_SPDIF 36
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#define CLK_AUDIO_DAC 37
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#define CLK_RPU_V 38
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#define CLK_RPU_L 39
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#define CLK_RPU_SLEEP 40
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#define CLK_WIFI_PLL_GATE 41
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#define CLK_RPU_CORE 42
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#define CLK_WIFI_ADC 43
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#define CLK_WIFI_DAC 44
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#define CLK_USB_PHY 45
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#define CLK_ENET_IN 46
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#define CLK_ENET 47
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#define CLK_UART0 48
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#define CLK_UART1 49
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#define CLK_PERIPH_SYS 50
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#define CLK_SPI0 51
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#define CLK_SPI1 52
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#define CLK_EVENT_TIMER 53
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#define CLK_AUX_ADC_INTERNAL 54
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#define CLK_AUX_ADC 55
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#define CLK_SD_HOST 56
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#define CLK_BT 57
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#define CLK_BT_DIV4 58
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#define CLK_BT_DIV8 59
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#define CLK_BT_1MHZ 60
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/* Divider clocks */
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#define CLK_MIPS_INTERNAL_DIV 64
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#define CLK_MIPS_DIV 65
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#define CLK_AUDIO_DIV 66
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#define CLK_I2S_DIV 67
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#define CLK_SPDIF_DIV 68
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#define CLK_AUDIO_DAC_DIV 69
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#define CLK_RPU_V_DIV 70
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#define CLK_RPU_L_DIV 71
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#define CLK_RPU_SLEEP_DIV 72
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#define CLK_RPU_CORE_DIV 73
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#define CLK_USB_PHY_DIV 74
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#define CLK_ENET_DIV 75
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#define CLK_UART0_INTERNAL_DIV 76
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#define CLK_UART0_DIV 77
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#define CLK_UART1_INTERNAL_DIV 78
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#define CLK_UART1_DIV 79
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#define CLK_SYS_INTERNAL_DIV 80
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#define CLK_SPI0_INTERNAL_DIV 81
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#define CLK_SPI0_DIV 82
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#define CLK_SPI1_INTERNAL_DIV 83
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#define CLK_SPI1_DIV 84
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#define CLK_EVENT_TIMER_INTERNAL_DIV 85
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#define CLK_EVENT_TIMER_DIV 86
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#define CLK_AUX_ADC_INTERNAL_DIV 87
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#define CLK_AUX_ADC_DIV 88
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#define CLK_SD_HOST_DIV 89
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#define CLK_BT_DIV 90
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#define CLK_BT_DIV4_DIV 91
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#define CLK_BT_DIV8_DIV 92
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#define CLK_BT_1MHZ_INTERNAL_DIV 93
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#define CLK_BT_1MHZ_DIV 94
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/* Mux clocks */
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#define CLK_AUDIO_REF_MUX 96
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#define CLK_MIPS_PLL_MUX 97
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#define CLK_AUDIO_PLL_MUX 98
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#define CLK_AUDIO_MUX 99
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#define CLK_RPU_V_PLL_MUX 100
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#define CLK_RPU_L_PLL_MUX 101
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#define CLK_RPU_L_MUX 102
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#define CLK_WIFI_PLL_MUX 103
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#define CLK_WIFI_DIV4_MUX 104
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#define CLK_WIFI_DIV8_MUX 105
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#define CLK_RPU_CORE_MUX 106
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#define CLK_SYS_PLL_MUX 107
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#define CLK_ENET_MUX 108
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#define CLK_EVENT_TIMER_MUX 109
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#define CLK_SD_HOST_MUX 110
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#define CLK_BT_PLL_MUX 111
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#define CLK_DEBUG_MUX 112
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#define CLK_NR_CLKS 113
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/* Peripheral gate clocks */
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#define PERIPH_CLK_SYS 0
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#define PERIPH_CLK_SYS_BUS 1
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#define PERIPH_CLK_DDR 2
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#define PERIPH_CLK_ROM 3
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#define PERIPH_CLK_COUNTER_FAST 4
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#define PERIPH_CLK_COUNTER_SLOW 5
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#define PERIPH_CLK_IR 6
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#define PERIPH_CLK_WD 7
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#define PERIPH_CLK_PDM 8
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#define PERIPH_CLK_PWM 9
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#define PERIPH_CLK_I2C0 10
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#define PERIPH_CLK_I2C1 11
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#define PERIPH_CLK_I2C2 12
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#define PERIPH_CLK_I2C3 13
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/* Peripheral divider clocks */
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#define PERIPH_CLK_ROM_DIV 32
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#define PERIPH_CLK_COUNTER_FAST_DIV 33
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#define PERIPH_CLK_COUNTER_SLOW_PRE_DIV 34
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#define PERIPH_CLK_COUNTER_SLOW_DIV 35
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#define PERIPH_CLK_IR_PRE_DIV 36
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#define PERIPH_CLK_IR_DIV 37
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#define PERIPH_CLK_WD_PRE_DIV 38
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#define PERIPH_CLK_WD_DIV 39
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#define PERIPH_CLK_PDM_PRE_DIV 40
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#define PERIPH_CLK_PDM_DIV 41
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#define PERIPH_CLK_PWM_PRE_DIV 42
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#define PERIPH_CLK_PWM_DIV 43
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#define PERIPH_CLK_I2C0_PRE_DIV 44
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#define PERIPH_CLK_I2C0_DIV 45
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#define PERIPH_CLK_I2C1_PRE_DIV 46
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#define PERIPH_CLK_I2C1_DIV 47
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#define PERIPH_CLK_I2C2_PRE_DIV 48
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#define PERIPH_CLK_I2C2_DIV 49
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#define PERIPH_CLK_I2C3_PRE_DIV 50
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#define PERIPH_CLK_I2C3_DIV 51
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#define PERIPH_CLK_NR_CLKS 52
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/* System gate clocks */
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#define SYS_CLK_I2C0 0
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#define SYS_CLK_I2C1 1
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#define SYS_CLK_I2C2 2
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#define SYS_CLK_I2C3 3
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#define SYS_CLK_I2S_IN 4
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#define SYS_CLK_PAUD_OUT 5
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#define SYS_CLK_SPDIF_OUT 6
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#define SYS_CLK_SPI0_MASTER 7
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#define SYS_CLK_SPI0_SLAVE 8
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#define SYS_CLK_PWM 9
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#define SYS_CLK_UART0 10
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#define SYS_CLK_UART1 11
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#define SYS_CLK_SPI1 12
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#define SYS_CLK_MDC 13
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#define SYS_CLK_SD_HOST 14
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#define SYS_CLK_ENET 15
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#define SYS_CLK_IR 16
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#define SYS_CLK_WD 17
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#define SYS_CLK_TIMER 18
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#define SYS_CLK_I2S_OUT 24
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#define SYS_CLK_SPDIF_IN 25
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#define SYS_CLK_EVENT_TIMER 26
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#define SYS_CLK_HASH 27
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#define SYS_CLK_NR_CLKS 28
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/* Gates for external input clocks */
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#define EXT_CLK_AUDIO_IN 0
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#define EXT_CLK_ENET_IN 1
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#define EXT_CLK_NR_CLKS 2
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#endif /* _DT_BINDINGS_CLOCK_PISTACHIO_H */
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