432 lines
9.9 KiB
C
432 lines
9.9 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* PCI Backend - Handles the virtual fields in the configuration space headers.
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*
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* Author: Ryan Wilson <hap9@epoch.ncsc.mil>
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#define dev_fmt pr_fmt
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include "pciback.h"
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#include "conf_space.h"
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struct pci_cmd_info {
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u16 val;
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};
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struct pci_bar_info {
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u32 val;
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u32 len_val;
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int which;
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};
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#define is_enable_cmd(value) ((value)&(PCI_COMMAND_MEMORY|PCI_COMMAND_IO))
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#define is_master_cmd(value) ((value)&PCI_COMMAND_MASTER)
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/* Bits guests are allowed to control in permissive mode. */
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#define PCI_COMMAND_GUEST (PCI_COMMAND_MASTER|PCI_COMMAND_SPECIAL| \
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PCI_COMMAND_INVALIDATE|PCI_COMMAND_VGA_PALETTE| \
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PCI_COMMAND_WAIT|PCI_COMMAND_FAST_BACK)
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static void *command_init(struct pci_dev *dev, int offset)
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{
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struct pci_cmd_info *cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
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int err;
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if (!cmd)
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return ERR_PTR(-ENOMEM);
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err = pci_read_config_word(dev, PCI_COMMAND, &cmd->val);
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if (err) {
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kfree(cmd);
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return ERR_PTR(err);
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}
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return cmd;
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}
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static int command_read(struct pci_dev *dev, int offset, u16 *value, void *data)
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{
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int ret = pci_read_config_word(dev, offset, value);
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const struct pci_cmd_info *cmd = data;
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*value &= PCI_COMMAND_GUEST;
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*value |= cmd->val & ~PCI_COMMAND_GUEST;
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return ret;
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}
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static int command_write(struct pci_dev *dev, int offset, u16 value, void *data)
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{
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struct xen_pcibk_dev_data *dev_data;
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int err;
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u16 val;
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struct pci_cmd_info *cmd = data;
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dev_data = pci_get_drvdata(dev);
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if (!pci_is_enabled(dev) && is_enable_cmd(value)) {
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dev_dbg(&dev->dev, "enable\n");
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err = pci_enable_device(dev);
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if (err)
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return err;
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if (dev_data)
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dev_data->enable_intx = 1;
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} else if (pci_is_enabled(dev) && !is_enable_cmd(value)) {
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dev_dbg(&dev->dev, "disable\n");
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pci_disable_device(dev);
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if (dev_data)
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dev_data->enable_intx = 0;
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}
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if (!dev->is_busmaster && is_master_cmd(value)) {
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dev_dbg(&dev->dev, "set bus master\n");
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pci_set_master(dev);
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} else if (dev->is_busmaster && !is_master_cmd(value)) {
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dev_dbg(&dev->dev, "clear bus master\n");
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pci_clear_master(dev);
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}
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if (!(cmd->val & PCI_COMMAND_INVALIDATE) &&
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(value & PCI_COMMAND_INVALIDATE)) {
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dev_dbg(&dev->dev, "enable memory-write-invalidate\n");
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err = pci_set_mwi(dev);
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if (err) {
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dev_warn(&dev->dev, "cannot enable memory-write-invalidate (%d)\n",
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err);
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value &= ~PCI_COMMAND_INVALIDATE;
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}
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} else if ((cmd->val & PCI_COMMAND_INVALIDATE) &&
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!(value & PCI_COMMAND_INVALIDATE)) {
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dev_dbg(&dev->dev, "disable memory-write-invalidate\n");
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pci_clear_mwi(dev);
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}
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if (dev_data && dev_data->allow_interrupt_control) {
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if ((cmd->val ^ value) & PCI_COMMAND_INTX_DISABLE) {
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if (value & PCI_COMMAND_INTX_DISABLE) {
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pci_intx(dev, 0);
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} else {
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/* Do not allow enabling INTx together with MSI or MSI-X. */
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switch (xen_pcibk_get_interrupt_type(dev)) {
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case INTERRUPT_TYPE_NONE:
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pci_intx(dev, 1);
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break;
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case INTERRUPT_TYPE_INTX:
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break;
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default:
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return PCIBIOS_SET_FAILED;
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}
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}
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}
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}
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cmd->val = value;
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if (!xen_pcibk_permissive && (!dev_data || !dev_data->permissive))
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return 0;
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/* Only allow the guest to control certain bits. */
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err = pci_read_config_word(dev, offset, &val);
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if (err || val == value)
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return err;
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value &= PCI_COMMAND_GUEST;
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value |= val & ~PCI_COMMAND_GUEST;
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return pci_write_config_word(dev, offset, value);
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}
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static int rom_write(struct pci_dev *dev, int offset, u32 value, void *data)
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{
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struct pci_bar_info *bar = data;
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if (unlikely(!bar)) {
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dev_warn(&dev->dev, "driver data not found\n");
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return XEN_PCI_ERR_op_failed;
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}
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/* A write to obtain the length must happen as a 32-bit write.
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* This does not (yet) support writing individual bytes
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*/
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if ((value | ~PCI_ROM_ADDRESS_MASK) == ~0U)
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bar->which = 1;
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else {
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u32 tmpval;
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pci_read_config_dword(dev, offset, &tmpval);
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if (tmpval != bar->val && value == bar->val) {
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/* Allow restoration of bar value. */
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pci_write_config_dword(dev, offset, bar->val);
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}
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bar->which = 0;
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}
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/* Do we need to support enabling/disabling the rom address here? */
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return 0;
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}
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/* For the BARs, only allow writes which write ~0 or
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* the correct resource information
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* (Needed for when the driver probes the resource usage)
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*/
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static int bar_write(struct pci_dev *dev, int offset, u32 value, void *data)
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{
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struct pci_bar_info *bar = data;
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unsigned int pos = (offset - PCI_BASE_ADDRESS_0) / 4;
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const struct resource *res = dev->resource;
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u32 mask;
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if (unlikely(!bar)) {
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dev_warn(&dev->dev, "driver data not found\n");
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return XEN_PCI_ERR_op_failed;
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}
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/* A write to obtain the length must happen as a 32-bit write.
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* This does not (yet) support writing individual bytes
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*/
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if (res[pos].flags & IORESOURCE_IO)
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mask = ~PCI_BASE_ADDRESS_IO_MASK;
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else if (pos && (res[pos - 1].flags & IORESOURCE_MEM_64))
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mask = 0;
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else
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mask = ~PCI_BASE_ADDRESS_MEM_MASK;
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if ((value | mask) == ~0U)
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bar->which = 1;
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else {
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u32 tmpval;
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pci_read_config_dword(dev, offset, &tmpval);
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if (tmpval != bar->val && value == bar->val) {
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/* Allow restoration of bar value. */
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pci_write_config_dword(dev, offset, bar->val);
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}
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bar->which = 0;
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}
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return 0;
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}
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static int bar_read(struct pci_dev *dev, int offset, u32 * value, void *data)
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{
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struct pci_bar_info *bar = data;
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if (unlikely(!bar)) {
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dev_warn(&dev->dev, "driver data not found\n");
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return XEN_PCI_ERR_op_failed;
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}
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*value = bar->which ? bar->len_val : bar->val;
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return 0;
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}
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static void *bar_init(struct pci_dev *dev, int offset)
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{
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unsigned int pos;
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const struct resource *res = dev->resource;
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struct pci_bar_info *bar = kzalloc(sizeof(*bar), GFP_KERNEL);
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if (!bar)
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return ERR_PTR(-ENOMEM);
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if (offset == PCI_ROM_ADDRESS || offset == PCI_ROM_ADDRESS1)
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pos = PCI_ROM_RESOURCE;
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else {
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pos = (offset - PCI_BASE_ADDRESS_0) / 4;
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if (pos && (res[pos - 1].flags & IORESOURCE_MEM_64)) {
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/*
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* Use ">> 16 >> 16" instead of direct ">> 32" shift
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* to avoid warnings on 32-bit architectures.
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*/
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bar->val = res[pos - 1].start >> 16 >> 16;
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bar->len_val = -resource_size(&res[pos - 1]) >> 16 >> 16;
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return bar;
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}
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}
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if (!res[pos].flags ||
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(res[pos].flags & (IORESOURCE_DISABLED | IORESOURCE_UNSET |
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IORESOURCE_BUSY)))
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return bar;
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bar->val = res[pos].start |
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(res[pos].flags & PCI_REGION_FLAG_MASK);
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bar->len_val = -resource_size(&res[pos]) |
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(res[pos].flags & PCI_REGION_FLAG_MASK);
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return bar;
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}
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static void bar_reset(struct pci_dev *dev, int offset, void *data)
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{
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struct pci_bar_info *bar = data;
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bar->which = 0;
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}
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static void bar_release(struct pci_dev *dev, int offset, void *data)
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{
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kfree(data);
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}
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static int xen_pcibk_read_vendor(struct pci_dev *dev, int offset,
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u16 *value, void *data)
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{
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*value = dev->vendor;
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return 0;
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}
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static int xen_pcibk_read_device(struct pci_dev *dev, int offset,
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u16 *value, void *data)
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{
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*value = dev->device;
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return 0;
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}
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static int interrupt_read(struct pci_dev *dev, int offset, u8 * value,
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void *data)
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{
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*value = (u8) dev->irq;
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return 0;
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}
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static int bist_write(struct pci_dev *dev, int offset, u8 value, void *data)
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{
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u8 cur_value;
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int err;
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err = pci_read_config_byte(dev, offset, &cur_value);
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if (err)
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goto out;
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if ((cur_value & ~PCI_BIST_START) == (value & ~PCI_BIST_START)
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|| value == PCI_BIST_START)
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err = pci_write_config_byte(dev, offset, value);
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out:
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return err;
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}
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static const struct config_field header_common[] = {
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{
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.offset = PCI_VENDOR_ID,
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.size = 2,
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.u.w.read = xen_pcibk_read_vendor,
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},
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{
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.offset = PCI_DEVICE_ID,
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.size = 2,
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.u.w.read = xen_pcibk_read_device,
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},
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{
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.offset = PCI_COMMAND,
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.size = 2,
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.init = command_init,
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.release = bar_release,
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.u.w.read = command_read,
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.u.w.write = command_write,
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},
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{
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.offset = PCI_INTERRUPT_LINE,
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.size = 1,
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.u.b.read = interrupt_read,
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},
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{
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.offset = PCI_INTERRUPT_PIN,
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.size = 1,
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.u.b.read = xen_pcibk_read_config_byte,
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},
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{
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/* Any side effects of letting driver domain control cache line? */
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.offset = PCI_CACHE_LINE_SIZE,
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.size = 1,
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.u.b.read = xen_pcibk_read_config_byte,
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.u.b.write = xen_pcibk_write_config_byte,
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},
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{
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.offset = PCI_LATENCY_TIMER,
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.size = 1,
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.u.b.read = xen_pcibk_read_config_byte,
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},
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{
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.offset = PCI_BIST,
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.size = 1,
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.u.b.read = xen_pcibk_read_config_byte,
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.u.b.write = bist_write,
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},
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{}
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};
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#define CFG_FIELD_BAR(reg_offset) \
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{ \
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.offset = reg_offset, \
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.size = 4, \
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.init = bar_init, \
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.reset = bar_reset, \
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.release = bar_release, \
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.u.dw.read = bar_read, \
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.u.dw.write = bar_write, \
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}
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#define CFG_FIELD_ROM(reg_offset) \
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{ \
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.offset = reg_offset, \
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.size = 4, \
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.init = bar_init, \
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.reset = bar_reset, \
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|
|
.release = bar_release, \
|
||
|
|
.u.dw.read = bar_read, \
|
||
|
|
.u.dw.write = rom_write, \
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct config_field header_0[] = {
|
||
|
|
CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
|
||
|
|
CFG_FIELD_BAR(PCI_BASE_ADDRESS_1),
|
||
|
|
CFG_FIELD_BAR(PCI_BASE_ADDRESS_2),
|
||
|
|
CFG_FIELD_BAR(PCI_BASE_ADDRESS_3),
|
||
|
|
CFG_FIELD_BAR(PCI_BASE_ADDRESS_4),
|
||
|
|
CFG_FIELD_BAR(PCI_BASE_ADDRESS_5),
|
||
|
|
CFG_FIELD_ROM(PCI_ROM_ADDRESS),
|
||
|
|
{}
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct config_field header_1[] = {
|
||
|
|
CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
|
||
|
|
CFG_FIELD_BAR(PCI_BASE_ADDRESS_1),
|
||
|
|
CFG_FIELD_ROM(PCI_ROM_ADDRESS1),
|
||
|
|
{}
|
||
|
|
};
|
||
|
|
|
||
|
|
int xen_pcibk_config_header_add_fields(struct pci_dev *dev)
|
||
|
|
{
|
||
|
|
int err;
|
||
|
|
|
||
|
|
err = xen_pcibk_config_add_fields(dev, header_common);
|
||
|
|
if (err)
|
||
|
|
goto out;
|
||
|
|
|
||
|
|
switch (dev->hdr_type) {
|
||
|
|
case PCI_HEADER_TYPE_NORMAL:
|
||
|
|
err = xen_pcibk_config_add_fields(dev, header_0);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PCI_HEADER_TYPE_BRIDGE:
|
||
|
|
err = xen_pcibk_config_add_fields(dev, header_1);
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
err = -EINVAL;
|
||
|
|
dev_err(&dev->dev, "Unsupported header type %d!\n",
|
||
|
|
dev->hdr_type);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
out:
|
||
|
|
return err;
|
||
|
|
}
|