273 lines
8.9 KiB
C
273 lines
8.9 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2021 NXP
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-imx.h"
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enum imx93_pads {
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IMX93_IOMUXC_DAP_TDI = 0,
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IMX93_IOMUXC_DAP_TMS_SWDIO = 1,
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IMX93_IOMUXC_DAP_TCLK_SWCLK = 2,
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IMX93_IOMUXC_DAP_TDO_TRACESWO = 3,
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IMX93_IOMUXC_GPIO_IO00 = 4,
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IMX93_IOMUXC_GPIO_IO01 = 5,
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IMX93_IOMUXC_GPIO_IO02 = 6,
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IMX93_IOMUXC_GPIO_IO03 = 7,
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IMX93_IOMUXC_GPIO_IO04 = 8,
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IMX93_IOMUXC_GPIO_IO05 = 9,
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IMX93_IOMUXC_GPIO_IO06 = 10,
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IMX93_IOMUXC_GPIO_IO07 = 11,
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IMX93_IOMUXC_GPIO_IO08 = 12,
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IMX93_IOMUXC_GPIO_IO09 = 13,
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IMX93_IOMUXC_GPIO_IO10 = 14,
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IMX93_IOMUXC_GPIO_IO11 = 15,
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IMX93_IOMUXC_GPIO_IO12 = 16,
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IMX93_IOMUXC_GPIO_IO13 = 17,
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IMX93_IOMUXC_GPIO_IO14 = 18,
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IMX93_IOMUXC_GPIO_IO15 = 19,
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IMX93_IOMUXC_GPIO_IO16 = 20,
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IMX93_IOMUXC_GPIO_IO17 = 21,
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IMX93_IOMUXC_GPIO_IO18 = 22,
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IMX93_IOMUXC_GPIO_IO19 = 23,
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IMX93_IOMUXC_GPIO_IO20 = 24,
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IMX93_IOMUXC_GPIO_IO21 = 25,
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IMX93_IOMUXC_GPIO_IO22 = 26,
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IMX93_IOMUXC_GPIO_IO23 = 27,
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IMX93_IOMUXC_GPIO_IO24 = 28,
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IMX93_IOMUXC_GPIO_IO25 = 29,
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IMX93_IOMUXC_GPIO_IO26 = 30,
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IMX93_IOMUXC_GPIO_IO27 = 31,
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IMX93_IOMUXC_GPIO_IO28 = 32,
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IMX93_IOMUXC_GPIO_IO29 = 33,
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IMX93_IOMUXC_CCM_CLKO1 = 34,
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IMX93_IOMUXC_CCM_CLKO2 = 35,
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IMX93_IOMUXC_CCM_CLKO3 = 36,
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IMX93_IOMUXC_CCM_CLKO4 = 37,
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IMX93_IOMUXC_ENET1_MDC = 38,
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IMX93_IOMUXC_ENET1_MDIO = 39,
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IMX93_IOMUXC_ENET1_TD3 = 40,
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IMX93_IOMUXC_ENET1_TD2 = 41,
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IMX93_IOMUXC_ENET1_TD1 = 42,
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IMX93_IOMUXC_ENET1_TD0 = 43,
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IMX93_IOMUXC_ENET1_TX_CTL = 44,
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IMX93_IOMUXC_ENET1_TXC = 45,
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IMX93_IOMUXC_ENET1_RX_CTL = 46,
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IMX93_IOMUXC_ENET1_RXC = 47,
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IMX93_IOMUXC_ENET1_RD0 = 48,
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IMX93_IOMUXC_ENET1_RD1 = 49,
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IMX93_IOMUXC_ENET1_RD2 = 50,
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IMX93_IOMUXC_ENET1_RD3 = 51,
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IMX93_IOMUXC_ENET2_MDC = 52,
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IMX93_IOMUXC_ENET2_MDIO = 53,
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IMX93_IOMUXC_ENET2_TD3 = 54,
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IMX93_IOMUXC_ENET2_TD2 = 55,
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IMX93_IOMUXC_ENET2_TD1 = 56,
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IMX93_IOMUXC_ENET2_TD0 = 57,
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IMX93_IOMUXC_ENET2_TX_CTL = 58,
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IMX93_IOMUXC_ENET2_TXC = 59,
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IMX93_IOMUXC_ENET2_RX_CTL = 60,
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IMX93_IOMUXC_ENET2_RXC = 61,
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IMX93_IOMUXC_ENET2_RD0 = 62,
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IMX93_IOMUXC_ENET2_RD1 = 63,
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IMX93_IOMUXC_ENET2_RD2 = 64,
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IMX93_IOMUXC_ENET2_RD3 = 65,
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IMX93_IOMUXC_SD1_CLK = 66,
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IMX93_IOMUXC_SD1_CMD = 67,
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IMX93_IOMUXC_SD1_DATA0 = 68,
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IMX93_IOMUXC_SD1_DATA1 = 69,
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IMX93_IOMUXC_SD1_DATA2 = 70,
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IMX93_IOMUXC_SD1_DATA3 = 71,
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IMX93_IOMUXC_SD1_DATA4 = 72,
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IMX93_IOMUXC_SD1_DATA5 = 73,
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IMX93_IOMUXC_SD1_DATA6 = 74,
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IMX93_IOMUXC_SD1_DATA7 = 75,
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IMX93_IOMUXC_SD1_STROBE = 76,
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IMX93_IOMUXC_SD2_VSELECT = 77,
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IMX93_IOMUXC_SD3_CLK = 78,
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IMX93_IOMUXC_SD3_CMD = 79,
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IMX93_IOMUXC_SD3_DATA0 = 80,
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IMX93_IOMUXC_SD3_DATA1 = 81,
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IMX93_IOMUXC_SD3_DATA2 = 82,
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IMX93_IOMUXC_SD3_DATA3 = 83,
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IMX93_IOMUXC_SD2_CD_B = 84,
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IMX93_IOMUXC_SD2_CLK = 85,
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IMX93_IOMUXC_SD2_CMD = 86,
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IMX93_IOMUXC_SD2_DATA0 = 87,
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IMX93_IOMUXC_SD2_DATA1 = 88,
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IMX93_IOMUXC_SD2_DATA2 = 89,
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IMX93_IOMUXC_SD2_DATA3 = 90,
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IMX93_IOMUXC_SD2_RESET_B = 91,
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IMX93_IOMUXC_I2C1_SCL = 92,
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IMX93_IOMUXC_I2C1_SDA = 93,
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IMX93_IOMUXC_I2C2_SCL = 94,
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IMX93_IOMUXC_I2C2_SDA = 95,
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IMX93_IOMUXC_UART1_RXD = 96,
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IMX93_IOMUXC_UART1_TXD = 97,
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IMX93_IOMUXC_UART2_RXD = 98,
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IMX93_IOMUXC_UART2_TXD = 99,
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IMX93_IOMUXC_PDM_CLK = 100,
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IMX93_IOMUXC_PDM_BIT_STREAM0 = 101,
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IMX93_IOMUXC_PDM_BIT_STREAM1 = 102,
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IMX93_IOMUXC_SAI1_TXFS = 103,
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IMX93_IOMUXC_SAI1_TXC = 104,
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IMX93_IOMUXC_SAI1_TXD0 = 105,
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IMX93_IOMUXC_SAI1_RXD0 = 106,
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IMX93_IOMUXC_WDOG_ANY = 107,
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};
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/* Pad names for the pinmux subsystem */
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static const struct pinctrl_pin_desc imx93_pinctrl_pads[] = {
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IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TDI),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TMS_SWDIO),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TCLK_SWCLK),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TDO_TRACESWO),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO00),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO01),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO02),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO03),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO04),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO05),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO06),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO07),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO08),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO09),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO10),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO11),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO12),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO13),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO14),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO15),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO16),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO17),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO18),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO19),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO20),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO21),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO22),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO23),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO24),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO25),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO26),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO27),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO28),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO29),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO1),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO2),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO3),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO4),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_MDC),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_MDIO),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD3),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD2),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD1),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD0),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TX_CTL),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TXC),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RX_CTL),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RXC),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD0),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD1),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD2),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD3),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_MDC),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_MDIO),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD3),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD2),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD1),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD0),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TX_CTL),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TXC),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RX_CTL),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RXC),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD0),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD1),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD2),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD3),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_CLK),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_CMD),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA0),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA1),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA2),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA3),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA4),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA5),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA6),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA7),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_STROBE),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_VSELECT),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_CLK),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_CMD),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA0),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA1),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA2),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA3),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_CD_B),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_CLK),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_CMD),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA0),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA1),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA2),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA3),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_RESET_B),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C1_SCL),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C1_SDA),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C2_SCL),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C2_SDA),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_UART1_RXD),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_UART1_TXD),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_UART2_RXD),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_UART2_TXD),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_PDM_CLK),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_PDM_BIT_STREAM0),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_PDM_BIT_STREAM1),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_TXFS),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_TXC),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_TXD0),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_RXD0),
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IMX_PINCTRL_PIN(IMX93_IOMUXC_WDOG_ANY),
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};
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static const struct imx_pinctrl_soc_info imx93_pinctrl_info = {
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.pins = imx93_pinctrl_pads,
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.npins = ARRAY_SIZE(imx93_pinctrl_pads),
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.gpr_compatible = "fsl,imx93-iomuxc-gpr",
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};
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static const struct of_device_id imx93_pinctrl_of_match[] = {
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{ .compatible = "fsl,imx93-iomuxc", },
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{ /* sentinel */ }
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};
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static int imx93_pinctrl_probe(struct platform_device *pdev)
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{
|
||
|
|
return imx_pinctrl_probe(pdev, &imx93_pinctrl_info);
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct platform_driver imx93_pinctrl_driver = {
|
||
|
|
.driver = {
|
||
|
|
.name = "imx93-pinctrl",
|
||
|
|
.of_match_table = imx93_pinctrl_of_match,
|
||
|
|
.suppress_bind_attrs = true,
|
||
|
|
},
|
||
|
|
.probe = imx93_pinctrl_probe,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int __init imx93_pinctrl_init(void)
|
||
|
|
{
|
||
|
|
return platform_driver_register(&imx93_pinctrl_driver);
|
||
|
|
}
|
||
|
|
arch_initcall(imx93_pinctrl_init);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Bai Ping <ping.bai@nxp.com>");
|
||
|
|
MODULE_DESCRIPTION("NXP i.MX93 pinctrl driver");
|
||
|
|
MODULE_LICENSE("GPL v2");
|