279 lines
7.5 KiB
C
279 lines
7.5 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2021 NXP
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-imx.h"
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enum imx8ulp_pads {
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IMX8ULP_PAD_PTD0 = 0,
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IMX8ULP_PAD_PTD1,
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IMX8ULP_PAD_PTD2,
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IMX8ULP_PAD_PTD3,
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IMX8ULP_PAD_PTD4,
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IMX8ULP_PAD_PTD5,
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IMX8ULP_PAD_PTD6,
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IMX8ULP_PAD_PTD7,
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IMX8ULP_PAD_PTD8,
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IMX8ULP_PAD_PTD9,
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IMX8ULP_PAD_PTD10,
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IMX8ULP_PAD_PTD11,
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IMX8ULP_PAD_PTD12,
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IMX8ULP_PAD_PTD13,
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IMX8ULP_PAD_PTD14,
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IMX8ULP_PAD_PTD15,
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IMX8ULP_PAD_PTD16,
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IMX8ULP_PAD_PTD17,
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IMX8ULP_PAD_PTD18,
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IMX8ULP_PAD_PTD19,
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IMX8ULP_PAD_PTD20,
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IMX8ULP_PAD_PTD21,
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IMX8ULP_PAD_PTD22,
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IMX8ULP_PAD_PTD23,
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IMX8ULP_PAD_RESERVE0,
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IMX8ULP_PAD_RESERVE1,
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IMX8ULP_PAD_RESERVE2,
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IMX8ULP_PAD_RESERVE3,
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IMX8ULP_PAD_RESERVE4,
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IMX8ULP_PAD_RESERVE5,
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IMX8ULP_PAD_RESERVE6,
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IMX8ULP_PAD_RESERVE7,
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IMX8ULP_PAD_PTE0,
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IMX8ULP_PAD_PTE1,
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IMX8ULP_PAD_PTE2,
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IMX8ULP_PAD_PTE3,
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IMX8ULP_PAD_PTE4,
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IMX8ULP_PAD_PTE5,
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IMX8ULP_PAD_PTE6,
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IMX8ULP_PAD_PTE7,
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IMX8ULP_PAD_PTE8,
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IMX8ULP_PAD_PTE9,
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IMX8ULP_PAD_PTE10,
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IMX8ULP_PAD_PTE11,
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IMX8ULP_PAD_PTE12,
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IMX8ULP_PAD_PTE13,
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IMX8ULP_PAD_PTE14,
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IMX8ULP_PAD_PTE15,
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IMX8ULP_PAD_PTE16,
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IMX8ULP_PAD_PTE17,
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IMX8ULP_PAD_PTE18,
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IMX8ULP_PAD_PTE19,
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IMX8ULP_PAD_PTE20,
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IMX8ULP_PAD_PTE21,
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IMX8ULP_PAD_PTE22,
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IMX8ULP_PAD_PTE23,
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IMX8ULP_PAD_RESERVE8,
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IMX8ULP_PAD_RESERVE9,
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IMX8ULP_PAD_RESERVE10,
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IMX8ULP_PAD_RESERVE11,
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IMX8ULP_PAD_RESERVE12,
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IMX8ULP_PAD_RESERVE13,
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IMX8ULP_PAD_RESERVE14,
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IMX8ULP_PAD_RESERVE15,
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IMX8ULP_PAD_PTF0,
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IMX8ULP_PAD_PTF1,
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IMX8ULP_PAD_PTF2,
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IMX8ULP_PAD_PTF3,
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IMX8ULP_PAD_PTF4,
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IMX8ULP_PAD_PTF5,
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IMX8ULP_PAD_PTF6,
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IMX8ULP_PAD_PTF7,
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IMX8ULP_PAD_PTF8,
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IMX8ULP_PAD_PTF9,
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IMX8ULP_PAD_PTF10,
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IMX8ULP_PAD_PTF11,
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IMX8ULP_PAD_PTF12,
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IMX8ULP_PAD_PTF13,
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IMX8ULP_PAD_PTF14,
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IMX8ULP_PAD_PTF15,
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IMX8ULP_PAD_PTF16,
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IMX8ULP_PAD_PTF17,
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IMX8ULP_PAD_PTF18,
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IMX8ULP_PAD_PTF19,
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IMX8ULP_PAD_PTF20,
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IMX8ULP_PAD_PTF21,
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IMX8ULP_PAD_PTF22,
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IMX8ULP_PAD_PTF23,
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IMX8ULP_PAD_PTF24,
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IMX8ULP_PAD_PTF25,
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IMX8ULP_PAD_PTF26,
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IMX8ULP_PAD_PTF27,
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IMX8ULP_PAD_PTF28,
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IMX8ULP_PAD_PTF29,
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IMX8ULP_PAD_PTF30,
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IMX8ULP_PAD_PTF31,
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};
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/* Pad names for the pinmux subsystem */
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static const struct pinctrl_pin_desc imx8ulp_pinctrl_pads[] = {
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD0),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD1),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD2),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD3),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD4),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD5),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD6),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD7),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD8),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD9),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD10),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD11),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD12),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD13),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD14),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD15),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD16),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD17),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD18),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD19),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD20),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD21),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD22),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD23),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE0),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE1),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE2),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE3),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE4),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE5),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE6),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE7),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE0),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE1),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE2),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE3),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE4),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE5),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE6),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE7),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE8),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE9),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE10),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE11),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE12),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE13),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE14),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE15),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE16),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE17),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE18),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE19),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE20),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE21),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE22),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE23),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE8),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE9),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE10),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE11),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE12),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE13),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE14),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE15),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF0),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF1),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF2),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF3),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF4),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF5),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF6),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF7),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF8),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF9),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF10),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF11),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF12),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF13),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF14),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF15),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF16),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF17),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF18),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF19),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF20),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF21),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF22),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF23),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF24),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF25),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF26),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF27),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF28),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF29),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF30),
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IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF31),
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};
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#define BM_OBE_ENABLED BIT(17)
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#define BM_IBE_ENABLED BIT(16)
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#define BM_MUX_MODE 0xf00
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#define BP_MUX_MODE 8
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static int imx8ulp_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned offset, bool input)
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{
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struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
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const struct imx_pin_reg *pin_reg;
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u32 reg;
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pin_reg = &ipctl->pin_regs[offset];
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if (pin_reg->mux_reg == -1)
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return -EINVAL;
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reg = readl(ipctl->base + pin_reg->mux_reg);
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if (input)
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reg = (reg & ~BM_OBE_ENABLED) | BM_IBE_ENABLED;
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else
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reg = (reg & ~BM_IBE_ENABLED) | BM_OBE_ENABLED;
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writel(reg, ipctl->base + pin_reg->mux_reg);
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return 0;
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}
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static const struct imx_pinctrl_soc_info imx8ulp_pinctrl_info = {
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.pins = imx8ulp_pinctrl_pads,
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.npins = ARRAY_SIZE(imx8ulp_pinctrl_pads),
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.flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,
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.gpio_set_direction = imx8ulp_pmx_gpio_set_direction,
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.mux_mask = BM_MUX_MODE,
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.mux_shift = BP_MUX_MODE,
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};
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static const struct of_device_id imx8ulp_pinctrl_of_match[] = {
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{ .compatible = "fsl,imx8ulp-iomuxc1", },
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{ /* sentinel */ }
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};
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static int imx8ulp_pinctrl_probe(struct platform_device *pdev)
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{
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return imx_pinctrl_probe(pdev, &imx8ulp_pinctrl_info);
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}
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static struct platform_driver imx8ulp_pinctrl_driver = {
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.driver = {
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.name = "imx8ulp-pinctrl",
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.of_match_table = imx8ulp_pinctrl_of_match,
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.suppress_bind_attrs = true,
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},
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.probe = imx8ulp_pinctrl_probe,
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};
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static int __init imx8ulp_pinctrl_init(void)
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{
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return platform_driver_register(&imx8ulp_pinctrl_driver);
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}
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arch_initcall(imx8ulp_pinctrl_init);
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MODULE_AUTHOR("Jacky Bai <ping.bai@nxp.com>");
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MODULE_DESCRIPTION("NXP i.MX8ULP pinctrl driver");
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MODULE_LICENSE("GPL v2");
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