271 lines
7.6 KiB
C
271 lines
7.6 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Marvell
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*
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* Authors:
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* Igal Liberman <igall@marvell.com>
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* Miquèl Raynal <miquel.raynal@bootlin.com>
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*
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* Marvell A3700 UTMI PHY driver
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*/
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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/* Armada 3700 UTMI PHY registers */
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#define USB2_PHY_PLL_CTRL_REG0 0x0
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#define PLL_REF_DIV_OFF 0
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#define PLL_REF_DIV_MASK GENMASK(6, 0)
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#define PLL_REF_DIV_5 5
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#define PLL_FB_DIV_OFF 16
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#define PLL_FB_DIV_MASK GENMASK(24, 16)
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#define PLL_FB_DIV_96 96
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#define PLL_SEL_LPFR_OFF 28
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#define PLL_SEL_LPFR_MASK GENMASK(29, 28)
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#define PLL_READY BIT(31)
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#define USB2_PHY_CAL_CTRL 0x8
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#define PHY_PLLCAL_DONE BIT(31)
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#define PHY_IMPCAL_DONE BIT(23)
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#define USB2_RX_CHAN_CTRL1 0x18
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#define USB2PHY_SQCAL_DONE BIT(31)
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#define USB2_PHY_OTG_CTRL 0x34
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#define PHY_PU_OTG BIT(4)
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#define USB2_PHY_CHRGR_DETECT 0x38
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#define PHY_CDP_EN BIT(2)
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#define PHY_DCP_EN BIT(3)
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#define PHY_PD_EN BIT(4)
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#define PHY_PU_CHRG_DTC BIT(5)
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#define PHY_CDP_DM_AUTO BIT(7)
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#define PHY_ENSWITCH_DP BIT(12)
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#define PHY_ENSWITCH_DM BIT(13)
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/* Armada 3700 USB miscellaneous registers */
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#define USB2_PHY_CTRL(usb32) (usb32 ? 0x20 : 0x4)
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#define RB_USB2PHY_PU BIT(0)
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#define USB2_DP_PULLDN_DEV_MODE BIT(5)
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#define USB2_DM_PULLDN_DEV_MODE BIT(6)
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#define RB_USB2PHY_SUSPM(usb32) (usb32 ? BIT(14) : BIT(7))
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#define PLL_LOCK_DELAY_US 10000
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#define PLL_LOCK_TIMEOUT_US 1000000
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/**
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* struct mvebu_a3700_utmi_caps - PHY capabilities
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*
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* @usb32: Flag indicating which PHY is in use (impacts the register map):
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* - The UTMI PHY wired to the USB3/USB2 controller (otg)
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* - The UTMI PHY wired to the USB2 controller (host only)
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* @ops: PHY operations
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*/
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struct mvebu_a3700_utmi_caps {
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int usb32;
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const struct phy_ops *ops;
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};
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/**
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* struct mvebu_a3700_utmi - PHY driver data
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*
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* @regs: PHY registers
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* @usb_misc: Regmap with USB miscellaneous registers including PHY ones
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* @caps: PHY capabilities
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* @phy: PHY handle
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*/
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struct mvebu_a3700_utmi {
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void __iomem *regs;
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struct regmap *usb_misc;
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const struct mvebu_a3700_utmi_caps *caps;
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struct phy *phy;
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};
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static int mvebu_a3700_utmi_phy_power_on(struct phy *phy)
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{
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struct mvebu_a3700_utmi *utmi = phy_get_drvdata(phy);
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struct device *dev = &phy->dev;
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int usb32 = utmi->caps->usb32;
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int ret = 0;
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u32 reg;
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/*
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* Setup PLL. 40MHz clock used to be the default, being 25MHz now.
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* See "PLL Settings for Typical REFCLK" table.
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*/
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reg = readl(utmi->regs + USB2_PHY_PLL_CTRL_REG0);
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reg &= ~(PLL_REF_DIV_MASK | PLL_FB_DIV_MASK | PLL_SEL_LPFR_MASK);
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reg |= (PLL_REF_DIV_5 << PLL_REF_DIV_OFF) |
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(PLL_FB_DIV_96 << PLL_FB_DIV_OFF);
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writel(reg, utmi->regs + USB2_PHY_PLL_CTRL_REG0);
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/* Enable PHY pull up and disable USB2 suspend */
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regmap_update_bits(utmi->usb_misc, USB2_PHY_CTRL(usb32),
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RB_USB2PHY_SUSPM(usb32) | RB_USB2PHY_PU,
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RB_USB2PHY_SUSPM(usb32) | RB_USB2PHY_PU);
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if (usb32) {
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/* Power up OTG module */
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reg = readl(utmi->regs + USB2_PHY_OTG_CTRL);
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reg |= PHY_PU_OTG;
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writel(reg, utmi->regs + USB2_PHY_OTG_CTRL);
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/* Disable PHY charger detection */
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reg = readl(utmi->regs + USB2_PHY_CHRGR_DETECT);
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reg &= ~(PHY_CDP_EN | PHY_DCP_EN | PHY_PD_EN | PHY_PU_CHRG_DTC |
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PHY_CDP_DM_AUTO | PHY_ENSWITCH_DP | PHY_ENSWITCH_DM);
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writel(reg, utmi->regs + USB2_PHY_CHRGR_DETECT);
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/* Disable PHY DP/DM pull-down (used for device mode) */
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regmap_update_bits(utmi->usb_misc, USB2_PHY_CTRL(usb32),
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USB2_DP_PULLDN_DEV_MODE |
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USB2_DM_PULLDN_DEV_MODE, 0);
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}
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/* Wait for PLL calibration */
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ret = readl_poll_timeout(utmi->regs + USB2_PHY_CAL_CTRL, reg,
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reg & PHY_PLLCAL_DONE,
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PLL_LOCK_DELAY_US, PLL_LOCK_TIMEOUT_US);
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if (ret) {
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dev_err(dev, "Failed to end USB2 PLL calibration\n");
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return ret;
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}
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/* Wait for impedance calibration */
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ret = readl_poll_timeout(utmi->regs + USB2_PHY_CAL_CTRL, reg,
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reg & PHY_IMPCAL_DONE,
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PLL_LOCK_DELAY_US, PLL_LOCK_TIMEOUT_US);
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if (ret) {
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dev_err(dev, "Failed to end USB2 impedance calibration\n");
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return ret;
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}
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/* Wait for squelch calibration */
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ret = readl_poll_timeout(utmi->regs + USB2_RX_CHAN_CTRL1, reg,
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reg & USB2PHY_SQCAL_DONE,
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PLL_LOCK_DELAY_US, PLL_LOCK_TIMEOUT_US);
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if (ret) {
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dev_err(dev, "Failed to end USB2 unknown calibration\n");
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return ret;
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}
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/* Wait for PLL to be locked */
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ret = readl_poll_timeout(utmi->regs + USB2_PHY_PLL_CTRL_REG0, reg,
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reg & PLL_READY,
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PLL_LOCK_DELAY_US, PLL_LOCK_TIMEOUT_US);
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if (ret)
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dev_err(dev, "Failed to lock USB2 PLL\n");
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return ret;
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}
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static int mvebu_a3700_utmi_phy_power_off(struct phy *phy)
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{
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struct mvebu_a3700_utmi *utmi = phy_get_drvdata(phy);
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int usb32 = utmi->caps->usb32;
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u32 reg;
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/* Disable PHY pull-up and enable USB2 suspend */
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reg = readl(utmi->regs + USB2_PHY_CTRL(usb32));
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reg &= ~(RB_USB2PHY_PU | RB_USB2PHY_SUSPM(usb32));
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writel(reg, utmi->regs + USB2_PHY_CTRL(usb32));
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/* Power down OTG module */
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if (usb32) {
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reg = readl(utmi->regs + USB2_PHY_OTG_CTRL);
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reg &= ~PHY_PU_OTG;
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writel(reg, utmi->regs + USB2_PHY_OTG_CTRL);
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}
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return 0;
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}
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static const struct phy_ops mvebu_a3700_utmi_phy_ops = {
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.power_on = mvebu_a3700_utmi_phy_power_on,
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.power_off = mvebu_a3700_utmi_phy_power_off,
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.owner = THIS_MODULE,
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};
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static const struct mvebu_a3700_utmi_caps mvebu_a3700_utmi_otg_phy_caps = {
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.usb32 = true,
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.ops = &mvebu_a3700_utmi_phy_ops,
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};
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static const struct mvebu_a3700_utmi_caps mvebu_a3700_utmi_host_phy_caps = {
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.usb32 = false,
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.ops = &mvebu_a3700_utmi_phy_ops,
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};
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static const struct of_device_id mvebu_a3700_utmi_of_match[] = {
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{
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.compatible = "marvell,a3700-utmi-otg-phy",
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.data = &mvebu_a3700_utmi_otg_phy_caps,
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},
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{
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.compatible = "marvell,a3700-utmi-host-phy",
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.data = &mvebu_a3700_utmi_host_phy_caps,
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, mvebu_a3700_utmi_of_match);
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static int mvebu_a3700_utmi_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mvebu_a3700_utmi *utmi;
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struct phy_provider *provider;
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utmi = devm_kzalloc(dev, sizeof(*utmi), GFP_KERNEL);
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if (!utmi)
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return -ENOMEM;
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/* Get UTMI memory region */
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utmi->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(utmi->regs))
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return PTR_ERR(utmi->regs);
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/* Get miscellaneous Host/PHY region */
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utmi->usb_misc = syscon_regmap_lookup_by_phandle(dev->of_node,
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"marvell,usb-misc-reg");
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if (IS_ERR(utmi->usb_misc)) {
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dev_err(dev,
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"Missing USB misc purpose system controller\n");
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return PTR_ERR(utmi->usb_misc);
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}
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/* Retrieve PHY capabilities */
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utmi->caps = of_device_get_match_data(dev);
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/* Instantiate the PHY */
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utmi->phy = devm_phy_create(dev, NULL, utmi->caps->ops);
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if (IS_ERR(utmi->phy)) {
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dev_err(dev, "Failed to create the UTMI PHY\n");
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return PTR_ERR(utmi->phy);
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}
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phy_set_drvdata(utmi->phy, utmi);
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/* Ensure the PHY is powered off */
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utmi->caps->ops->power_off(utmi->phy);
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provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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return PTR_ERR_OR_ZERO(provider);
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}
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static struct platform_driver mvebu_a3700_utmi_driver = {
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.probe = mvebu_a3700_utmi_phy_probe,
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.driver = {
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.name = "mvebu-a3700-utmi-phy",
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.of_match_table = mvebu_a3700_utmi_of_match,
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},
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};
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module_platform_driver(mvebu_a3700_utmi_driver);
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MODULE_AUTHOR("Igal Liberman <igall@marvell.com>");
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MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>");
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MODULE_DESCRIPTION("Marvell EBU A3700 UTMI PHY driver");
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MODULE_LICENSE("GPL v2");
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