530 lines
16 KiB
C
530 lines
16 KiB
C
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/* Copyright(c) 2019-2022 Realtek Corporation
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*/
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#include "debug.h"
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#include "fw.h"
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#include "mac.h"
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#include "phy.h"
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#include "reg.h"
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#include "rtw8852c.h"
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static const struct rtw89_dle_mem rtw8852c_dle_mem_pcie[] = {
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[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_wde_size19, &rtw89_ple_size19,
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&rtw89_wde_qt18, &rtw89_wde_qt18, &rtw89_ple_qt46,
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&rtw89_ple_qt47},
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[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_wde_size18,
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&rtw89_ple_size18, &rtw89_wde_qt17, &rtw89_wde_qt17,
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&rtw89_ple_qt44, &rtw89_ple_qt45},
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[RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
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NULL},
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};
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static const u32 rtw8852c_h2c_regs[RTW89_H2CREG_MAX] = {
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R_AX_H2CREG_DATA0_V1, R_AX_H2CREG_DATA1_V1, R_AX_H2CREG_DATA2_V1,
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R_AX_H2CREG_DATA3_V1
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};
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static const u32 rtw8852c_c2h_regs[RTW89_H2CREG_MAX] = {
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R_AX_C2HREG_DATA0_V1, R_AX_C2HREG_DATA1_V1, R_AX_C2HREG_DATA2_V1,
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R_AX_C2HREG_DATA3_V1
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};
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static const struct rtw89_page_regs rtw8852c_page_regs = {
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.hci_fc_ctrl = R_AX_HCI_FC_CTRL_V1,
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.ch_page_ctrl = R_AX_CH_PAGE_CTRL_V1,
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.ach_page_ctrl = R_AX_ACH0_PAGE_CTRL_V1,
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.ach_page_info = R_AX_ACH0_PAGE_INFO_V1,
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.pub_page_info3 = R_AX_PUB_PAGE_INFO3_V1,
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.pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1_V1,
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.pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2_V1,
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.pub_page_info1 = R_AX_PUB_PAGE_INFO1_V1,
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.pub_page_info2 = R_AX_PUB_PAGE_INFO2_V1,
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.wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1_V1,
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.wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2_V1,
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.wp_page_info1 = R_AX_WP_PAGE_INFO1_V1,
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};
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static const struct rtw89_reg_def rtw8852c_dcfo_comp = {
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R_DCFO_COMP_S0_V1, B_DCFO_COMP_S0_V1_MSK
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};
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static int rtw8852c_pwr_on_func(struct rtw89_dev *rtwdev)
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{
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u32 val32;
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u32 ret;
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val32 = rtw89_read32_mask(rtwdev, R_AX_SYS_STATUS1, B_AX_PAD_HCI_SEL_V2_MASK);
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if (val32 == MAC_AX_HCI_SEL_PCIE_USB)
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rtw89_write32_set(rtwdev, R_AX_LDO_AON_CTRL0, B_AX_PD_REGU_L);
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rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN |
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B_AX_AFSM_PCIE_SUS_EN);
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rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC);
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rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC);
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rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN);
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rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
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ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR,
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1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
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if (ret)
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return ret;
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rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
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rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC);
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ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC),
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1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
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if (ret)
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return ret;
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rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
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rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
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rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
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rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
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rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
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rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1);
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rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_CMAC1_FEN);
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rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_R_SYM_ISO_CMAC12PP);
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rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, B_AX_R_SYM_WLCMAC1_P4_PC_EN |
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B_AX_R_SYM_WLCMAC1_P3_PC_EN |
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B_AX_R_SYM_WLCMAC1_P2_PC_EN |
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B_AX_R_SYM_WLCMAC1_P1_PC_EN |
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B_AX_R_SYM_WLCMAC1_PC_EN);
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rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3);
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL,
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XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL);
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if (ret)
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return ret;
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rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3);
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL,
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XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL);
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if (ret)
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return ret;
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI,
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XTAL_SI_OFF_WEI);
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if (ret)
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return ret;
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI,
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XTAL_SI_OFF_EI);
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if (ret)
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return ret;
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF);
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if (ret)
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return ret;
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI,
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XTAL_SI_PON_WEI);
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if (ret)
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return ret;
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI,
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XTAL_SI_PON_EI);
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if (ret)
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return ret;
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC);
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if (ret)
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return ret;
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS);
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if (ret)
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return ret;
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP);
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if (ret)
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return ret;
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rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
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rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE);
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rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15);
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fsleep(1000);
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rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
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rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
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rtw89_write32_set(rtwdev, R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN,
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B_AX_EECS_PULL_LOW_EN | B_AX_EESK_PULL_LOW_EN |
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B_AX_LED1_PULL_LOW_EN);
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rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
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B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN |
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B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN |
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B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN |
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B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN |
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B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN |
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B_AX_MAC_UN_EN | B_AX_H_AXIDMA_EN);
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rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN,
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B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN |
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B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN |
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B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN |
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B_AX_TMAC_EN | B_AX_RMAC_EN);
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return 0;
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}
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static int rtw8852c_pwr_off_func(struct rtw89_dev *rtwdev)
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{
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u32 val32;
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u32 ret;
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF,
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XTAL_SI_RFC2RF);
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if (ret)
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return ret;
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI);
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if (ret)
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return ret;
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI);
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if (ret)
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return ret;
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00);
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if (ret)
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return ret;
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10);
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if (ret)
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return ret;
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC,
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XTAL_SI_SRAM2RFC);
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if (ret)
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return ret;
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI);
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if (ret)
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return ret;
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI);
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if (ret)
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return ret;
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rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
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rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB);
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rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
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B_AX_R_SYM_FEN_WLBBGLB_1 | B_AX_R_SYM_FEN_WLBBFUN_1);
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rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3);
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL);
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if (ret)
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return ret;
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rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3);
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL);
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if (ret)
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return ret;
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rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC);
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ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC),
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1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
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if (ret)
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return ret;
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rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, 0x0001A0B0);
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rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_XTAL_OFF_A_DIE);
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rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
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return 0;
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}
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static void rtw8852c_e_efuse_parsing(struct rtw89_efuse *efuse,
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struct rtw8852c_efuse *map)
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{
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ether_addr_copy(efuse->addr, map->e.mac_addr);
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efuse->rfe_type = map->rfe_type;
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efuse->xtal_cap = map->xtal_k;
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}
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static void rtw8852c_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
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struct rtw8852c_efuse *map)
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{
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struct rtw89_tssi_info *tssi = &rtwdev->tssi;
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struct rtw8852c_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi};
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u8 *bw40_1s_tssi_6g_ofst[] = {map->bw40_1s_tssi_6g_a, map->bw40_1s_tssi_6g_b};
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u8 i, j;
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tssi->thermal[RF_PATH_A] = map->path_a_therm;
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tssi->thermal[RF_PATH_B] = map->path_b_therm;
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for (i = 0; i < RF_PATH_NUM_8852C; i++) {
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memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi,
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sizeof(ofst[i]->cck_tssi));
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for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
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rtw89_debug(rtwdev, RTW89_DBG_TSSI,
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"[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
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i, j, tssi->tssi_cck[i][j]);
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memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
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sizeof(ofst[i]->bw40_tssi));
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memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
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ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g));
|
||
|
|
memcpy(tssi->tssi_6g_mcs[i], bw40_1s_tssi_6g_ofst[i],
|
||
|
|
sizeof(tssi->tssi_6g_mcs[i]));
|
||
|
|
|
||
|
|
for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
|
||
|
|
rtw89_debug(rtwdev, RTW89_DBG_TSSI,
|
||
|
|
"[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
|
||
|
|
i, j, tssi->tssi_mcs[i][j]);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static int rtw8852c_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map)
|
||
|
|
{
|
||
|
|
struct rtw89_efuse *efuse = &rtwdev->efuse;
|
||
|
|
struct rtw8852c_efuse *map;
|
||
|
|
|
||
|
|
map = (struct rtw8852c_efuse *)log_map;
|
||
|
|
|
||
|
|
efuse->country_code[0] = map->country_code[0];
|
||
|
|
efuse->country_code[1] = map->country_code[1];
|
||
|
|
rtw8852c_efuse_parsing_tssi(rtwdev, map);
|
||
|
|
|
||
|
|
switch (rtwdev->hci.type) {
|
||
|
|
case RTW89_HCI_TYPE_PCIE:
|
||
|
|
rtw8852c_e_efuse_parsing(efuse, map);
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
return -ENOTSUPP;
|
||
|
|
}
|
||
|
|
|
||
|
|
rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void rtw8852c_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
|
||
|
|
{
|
||
|
|
struct rtw89_tssi_info *tssi = &rtwdev->tssi;
|
||
|
|
static const u32 tssi_trim_addr[RF_PATH_NUM_8852C] = {0x5D6, 0x5AB};
|
||
|
|
static const u32 tssi_trim_addr_6g[RF_PATH_NUM_8852C] = {0x5CE, 0x5A3};
|
||
|
|
u32 addr = rtwdev->chip->phycap_addr;
|
||
|
|
bool pg = false;
|
||
|
|
u32 ofst;
|
||
|
|
u8 i, j;
|
||
|
|
|
||
|
|
for (i = 0; i < RF_PATH_NUM_8852C; i++) {
|
||
|
|
for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) {
|
||
|
|
/* addrs are in decreasing order */
|
||
|
|
ofst = tssi_trim_addr[i] - addr - j;
|
||
|
|
tssi->tssi_trim[i][j] = phycap_map[ofst];
|
||
|
|
|
||
|
|
if (phycap_map[ofst] != 0xff)
|
||
|
|
pg = true;
|
||
|
|
}
|
||
|
|
|
||
|
|
for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM_6G; j++) {
|
||
|
|
/* addrs are in decreasing order */
|
||
|
|
ofst = tssi_trim_addr_6g[i] - addr - j;
|
||
|
|
tssi->tssi_trim_6g[i][j] = phycap_map[ofst];
|
||
|
|
|
||
|
|
if (phycap_map[ofst] != 0xff)
|
||
|
|
pg = true;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!pg) {
|
||
|
|
memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim));
|
||
|
|
memset(tssi->tssi_trim_6g, 0, sizeof(tssi->tssi_trim_6g));
|
||
|
|
rtw89_debug(rtwdev, RTW89_DBG_TSSI,
|
||
|
|
"[TSSI][TRIM] no PG, set all trim info to 0\n");
|
||
|
|
}
|
||
|
|
|
||
|
|
for (i = 0; i < RF_PATH_NUM_8852C; i++)
|
||
|
|
for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++)
|
||
|
|
rtw89_debug(rtwdev, RTW89_DBG_TSSI,
|
||
|
|
"[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",
|
||
|
|
i, j, tssi->tssi_trim[i][j],
|
||
|
|
tssi_trim_addr[i] - j);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void rtw8852c_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
|
||
|
|
u8 *phycap_map)
|
||
|
|
{
|
||
|
|
struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
|
||
|
|
static const u32 thm_trim_addr[RF_PATH_NUM_8852C] = {0x5DF, 0x5DC};
|
||
|
|
u32 addr = rtwdev->chip->phycap_addr;
|
||
|
|
u8 i;
|
||
|
|
|
||
|
|
for (i = 0; i < RF_PATH_NUM_8852C; i++) {
|
||
|
|
info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr];
|
||
|
|
|
||
|
|
rtw89_debug(rtwdev, RTW89_DBG_RFK,
|
||
|
|
"[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",
|
||
|
|
i, info->thermal_trim[i]);
|
||
|
|
|
||
|
|
if (info->thermal_trim[i] != 0xff)
|
||
|
|
info->pg_thermal_trim = true;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void rtw8852c_thermal_trim(struct rtw89_dev *rtwdev)
|
||
|
|
{
|
||
|
|
#define __thm_setting(raw) \
|
||
|
|
({ \
|
||
|
|
u8 __v = (raw); \
|
||
|
|
((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \
|
||
|
|
})
|
||
|
|
struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
|
||
|
|
u8 i, val;
|
||
|
|
|
||
|
|
if (!info->pg_thermal_trim) {
|
||
|
|
rtw89_debug(rtwdev, RTW89_DBG_RFK,
|
||
|
|
"[THERMAL][TRIM] no PG, do nothing\n");
|
||
|
|
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
for (i = 0; i < RF_PATH_NUM_8852C; i++) {
|
||
|
|
val = __thm_setting(info->thermal_trim[i]);
|
||
|
|
rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
|
||
|
|
|
||
|
|
rtw89_debug(rtwdev, RTW89_DBG_RFK,
|
||
|
|
"[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
|
||
|
|
i, val);
|
||
|
|
}
|
||
|
|
#undef __thm_setting
|
||
|
|
}
|
||
|
|
|
||
|
|
static void rtw8852c_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
|
||
|
|
u8 *phycap_map)
|
||
|
|
{
|
||
|
|
struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
|
||
|
|
static const u32 pabias_trim_addr[RF_PATH_NUM_8852C] = {0x5DE, 0x5DB};
|
||
|
|
u32 addr = rtwdev->chip->phycap_addr;
|
||
|
|
u8 i;
|
||
|
|
|
||
|
|
for (i = 0; i < RF_PATH_NUM_8852C; i++) {
|
||
|
|
info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
|
||
|
|
|
||
|
|
rtw89_debug(rtwdev, RTW89_DBG_RFK,
|
||
|
|
"[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
|
||
|
|
i, info->pa_bias_trim[i]);
|
||
|
|
|
||
|
|
if (info->pa_bias_trim[i] != 0xff)
|
||
|
|
info->pg_pa_bias_trim = true;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void rtw8852c_pa_bias_trim(struct rtw89_dev *rtwdev)
|
||
|
|
{
|
||
|
|
struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
|
||
|
|
u8 pabias_2g, pabias_5g;
|
||
|
|
u8 i;
|
||
|
|
|
||
|
|
if (!info->pg_pa_bias_trim) {
|
||
|
|
rtw89_debug(rtwdev, RTW89_DBG_RFK,
|
||
|
|
"[PA_BIAS][TRIM] no PG, do nothing\n");
|
||
|
|
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
for (i = 0; i < RF_PATH_NUM_8852C; i++) {
|
||
|
|
pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]);
|
||
|
|
pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]);
|
||
|
|
|
||
|
|
rtw89_debug(rtwdev, RTW89_DBG_RFK,
|
||
|
|
"[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
|
||
|
|
i, pabias_2g, pabias_5g);
|
||
|
|
|
||
|
|
rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
|
||
|
|
rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static int rtw8852c_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
|
||
|
|
{
|
||
|
|
rtw8852c_phycap_parsing_tssi(rtwdev, phycap_map);
|
||
|
|
rtw8852c_phycap_parsing_thermal_trim(rtwdev, phycap_map);
|
||
|
|
rtw8852c_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void rtw8852c_power_trim(struct rtw89_dev *rtwdev)
|
||
|
|
{
|
||
|
|
rtw8852c_thermal_trim(rtwdev);
|
||
|
|
rtw8852c_pa_bias_trim(rtwdev);
|
||
|
|
}
|
||
|
|
|
||
|
|
static
|
||
|
|
void rtw8852c_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
|
||
|
|
s8 pw_ofst, enum rtw89_mac_idx mac_idx)
|
||
|
|
{
|
||
|
|
s8 pw_ofst_2tx;
|
||
|
|
s8 val_1t;
|
||
|
|
s8 val_2t;
|
||
|
|
u32 reg;
|
||
|
|
u8 i;
|
||
|
|
|
||
|
|
if (pw_ofst < -32 || pw_ofst > 31) {
|
||
|
|
rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
val_1t = pw_ofst << 2;
|
||
|
|
pw_ofst_2tx = max(pw_ofst - 3, -32);
|
||
|
|
val_2t = pw_ofst_2tx << 2;
|
||
|
|
|
||
|
|
rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_1tx=0x%x\n", val_1t);
|
||
|
|
rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_2tx=0x%x\n", val_2t);
|
||
|
|
|
||
|
|
for (i = 0; i < 4; i++) {
|
||
|
|
/* 1TX */
|
||
|
|
reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_1T, mac_idx);
|
||
|
|
rtw89_write32_mask(rtwdev, reg,
|
||
|
|
B_AX_PWR_UL_TB_1T_V1_MASK << (8 * i),
|
||
|
|
val_1t);
|
||
|
|
/* 2TX */
|
||
|
|
reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_2T, mac_idx);
|
||
|
|
rtw89_write32_mask(rtwdev, reg,
|
||
|
|
B_AX_PWR_UL_TB_2T_V1_MASK << (8 * i),
|
||
|
|
val_2t);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct rtw89_chip_ops rtw8852c_chip_ops = {
|
||
|
|
.read_efuse = rtw8852c_read_efuse,
|
||
|
|
.read_phycap = rtw8852c_read_phycap,
|
||
|
|
.power_trim = rtw8852c_power_trim,
|
||
|
|
.read_rf = rtw89_phy_read_rf_v1,
|
||
|
|
.write_rf = rtw89_phy_write_rf_v1,
|
||
|
|
.set_txpwr_ul_tb_offset = rtw8852c_set_txpwr_ul_tb_offset,
|
||
|
|
.pwr_on_func = rtw8852c_pwr_on_func,
|
||
|
|
.pwr_off_func = rtw8852c_pwr_off_func,
|
||
|
|
.cfg_ctrl_path = rtw89_mac_cfg_ctrl_path_v1,
|
||
|
|
.mac_cfg_gnt = rtw89_mac_cfg_gnt_v1,
|
||
|
|
.stop_sch_tx = rtw89_mac_stop_sch_tx_v1,
|
||
|
|
.resume_sch_tx = rtw89_mac_resume_sch_tx_v1,
|
||
|
|
};
|
||
|
|
|
||
|
|
const struct rtw89_chip_info rtw8852c_chip_info = {
|
||
|
|
.chip_id = RTL8852C,
|
||
|
|
.ops = &rtw8852c_chip_ops,
|
||
|
|
.fw_name = "rtw89/rtw8852c_fw.bin",
|
||
|
|
.dle_mem = rtw8852c_dle_mem_pcie,
|
||
|
|
.rf_base_addr = {0xe000, 0xf000},
|
||
|
|
.pwr_on_seq = NULL,
|
||
|
|
.pwr_off_seq = NULL,
|
||
|
|
.sec_ctrl_efuse_size = 4,
|
||
|
|
.physical_efuse_size = 1216,
|
||
|
|
.logical_efuse_size = 2048,
|
||
|
|
.limit_efuse_size = 1280,
|
||
|
|
.dav_phy_efuse_size = 96,
|
||
|
|
.dav_log_efuse_size = 16,
|
||
|
|
.phycap_addr = 0x590,
|
||
|
|
.phycap_size = 0x60,
|
||
|
|
.hci_func_en_addr = R_AX_HCI_FUNC_EN_V1,
|
||
|
|
.h2c_ctrl_reg = R_AX_H2CREG_CTRL_V1,
|
||
|
|
.h2c_regs = rtw8852c_h2c_regs,
|
||
|
|
.c2h_ctrl_reg = R_AX_C2HREG_CTRL_V1,
|
||
|
|
.c2h_regs = rtw8852c_c2h_regs,
|
||
|
|
.page_regs = &rtw8852c_page_regs,
|
||
|
|
.dcfo_comp = &rtw8852c_dcfo_comp,
|
||
|
|
.dcfo_comp_sft = 5,
|
||
|
|
};
|
||
|
|
EXPORT_SYMBOL(rtw8852c_chip_info);
|
||
|
|
|
||
|
|
MODULE_FIRMWARE("rtw89/rtw8852c_fw.bin");
|
||
|
|
MODULE_AUTHOR("Realtek Corporation");
|
||
|
|
MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852C driver");
|
||
|
|
MODULE_LICENSE("Dual BSD/GPL");
|